I love getting Real demos from real engineers.
Last week, at Altera, I had the privilege of going into a real lab – where a real engineer was working – to see a Real demo.
For an editor, a Real demo is a rare pleasure. 99.99% of the demonstrations we editors see are Marketing demos, which are about as far from Real as you can get. We start with a few PowerPoint slides to “orient” us to what we’re about to see, then we get walked through a few carefully choreographed, canned operations where we are led to a conclusion that was obvious before we started. A typical Marketing demo script might be something like “Here, we’ve designed a board that has both our chip and our competitor’s chip. We’ve got them both loaded with (trust us on this) the exact same design. Now, if you look at the voltage across this resistor, you can clearly see that our device is using 30% less power. Here – you can even touch the probe to the trace yourself!”
Trusting an editor to touch a voltmeter probe to the end of a resistor is about the most high-wire, cliff-hanger risk you’ll ever find in a Marketing demo. What if we weren’t grounded properly? What if we ham-handed the meter and accidentally changed the scale? The implications are simply horrifying!
What you don’t, then, trust an editor to do is the simple arithmetic to get power from the resistor voltages. You have a pre-printed chart with – surprise! – the exact readings the editor gets from the two resistors, showing what power that represents – and calculating the 30.9% difference for the editor, lest there be any embarassing confusion, or the wrong denominator. Seriously, they should just silkscreen the numbers onto the multi-meter display. Are we editors really that gullible?
Altera’s demo last week was completely different. It was the Real deal. We were escorted into a real lab with a real engineer running real equipment. We interrupted his work. He had to move around some connections to show what we wanted to see, and then it didn’t work right at first. “Hmmm… it should be… no… Ah, here we go, this is connected to the wrong output. Give me a minute here.”
That sequence of events may have caused missed heartbeats and cold sweats from the Altera PR and marketing guys. For me, however, as an editor, it meant I was about to see something I seldom see… the truth. After a little fiddling with connectors, re-booting of boards, and adjusting of scopes, we got what we were looking for – a not-super-clean-but-clearly-open eye diagram which, when measured, showed the SerDes channel operating at just under 25 Gbps.
25Gbps SerDes is a big deal. With backplane bandwidth demands driving a never-ending road toward insane, we can’t just pack more wires in parallel. We need higher data rates on the wires we’ve already got. In their upcoming 28nm Stratix V family, Altera is determined to make that number 28 Gbps per channel. This demo, with an early test-chip, shows that they’re well on their way.
Competitively, 28nm will be an interesting process node in the FPGA business for several reasons. It marks the consolidation of Xilinx and Altera both getting their chips from the same supplier – TSMC. With that similarity, however, comes an important difference: Altera chose the high-speed process, and Xilinx chose the high-speed/low-power process. Xilinx claims that their choice is the only way to get the power density down so they can deliver the enormous devices they’ve promised at 28nm. Altera claims that their choice is the only way they can deliver blazing-fast 28 Gbps transceivers to meet the industry’s growing bandwidth needs. With realistically about a year before we have much exposure to the results of those claims, the jury is still out, but it will be an interesting ride.
Altera has spent their marketing energy thus far talking about bandwidth. Every word they speak ties back to delivering more bandwidth at higher rates with less power. Xilinx messaging seems focused on the expanding FPGA market, emphasizing a broad range of devices and design kits that expand FPGAs into new businesses and into more applications in existing ones. Behind both messages are very similar future FPGA families with far more in common than either vendor wants to admit. Realistically, the difference in their market success may not have much to do with the differences in devices themselves.
For Altera’s part, however, they’re headed full-tilt boogie down the bandwidth path. They are clearly still in the test-chip phase, and the test chips they’ve got right now show that the promised 28 Gpbs transceivers are in their grasp. Along with those speedy SerDes comes a raft of new features, including a cool built-in measurement capability (dubbed EyeQ) that lets you see the eye diagram from inside the transceiver – maybe saving yourself 100K or so on test gear. If you’re in the part of the FPGA market that cares the most about how many bits you can blast across existing backplanes, or how you’re going to connect up to 100G and eventually 400G optical modules, this can be nothing but good news for you.
If you’re the part of the FPGA market that is new to FPGA technology, or is interested in how many ASIC-equivalent gates you can pack in a programmable device, or wants to finish your multi-million-gate design without writing a lot of VHDL, super-speed transceivers may be just one checkmark in a long list. The rest of your list will have to wait for future editor demos, both Real and Marketing, to flesh out the reality of the 28nm FPGAs we’ll get to play with in a year or so. Programmable logic is cutting a wider and wider swath through the semiconductor field, and 28nm promises to widen that path once again. You can bet your bandwidth on it.