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Aldec Turns up the Simulation Heat

In many markets, there is what marketers call a “gorilla” – a company with a commanding market share that controls the way the ball rolls in that particular segment.  In HDL simulation for FPGAs, one could argue that ModelSim from Mentor Graphics has historically been the gorilla – with a dominant market share and OEM deals with most of the major FPGA vendors that allow them to be the first simulator out of the box when new designers start working on an FPGA design.

Aldec, Inc. has always played the role of spoiler to ModelSim’s gorilla.  From the sidelines, it appeared that Aldec generally employed the “fast follower” strategy – running close behind with new features and innovations and working to win on price.  The strategy worked relatively well for Aldec, who has kept a strong market share for over a decade. 

Now, however, Aldec has morphed into something more.  Not content to skate along sweeping up the table scraps, the company has evolved their simulation offering into a first-rate verification platform with all the bells and whistles (and, if you don’t verify your design with bells and whistles, it also has the power-user features you’d expect from a high-end multi-language verification environment).  Obviously not content to be the also-ran, or even just to compete solely in the FPGA arena, Aldec has bolstered their tools with significant capabilities and conjured up a clever marketing strategy to boot.

Aldec’s product lineup begins with the FPGA-centric Active-HDL (current version 8.2).  Active HDL includes a robust set of design creation tools as well as simulation/verification.  The first of these is a schematic/block-diagram editor that allows you to graphically create your HDL design (VHDL, Verilog, or even EDIF – for those of you that design in EDIF) and to visualize the structure and connectivity.  Of course “real” designers never use graphical entry tools, but if your design is structural, graphical entry can dramatically simplify the process of creating structure that actually makes sense.  (TIP:  You can make a “cover up” image that looks like you’re manually examining your FPGA bitstream in vi to pop up over the graphical window when one of your peers walks by.  They won’t know you’re using a graphical editor, and they’ll be duly impressed by your obvious skills.  This won’t work if you’re still using a VT-52 for your main terminal at work, of course.)  If you didn’t start out in graphics, you can use the “code2graphics” feature to convert your existing HDL to a graphical representation.  (At night, of course, when nobody is looking.)

Along those same lines, there is a graphical state machine editor that makes creating and visualizing state machines a snap.  It does just what you’d hope – you draw bubble diagrams with states and transitions – you can choose your flavor between Mealy and Moore – and it then compiles them into handsome synthesizable HDL.  It will also generate a testbench to be sure your state machine is ready for prime time.

Active-HDL also includes an “FPGA Project Manager,” which can control your entire design flow for FPGA design – including vendor and other third-party tools.  If you’re a “design cockpit” kinda designer and you don’t already have one you love – this one is worth a look.  In general, there is a tendency for every vendor to assume that their tools will be the center of your design universe, and they’ll to try to subsume all the other steps into their flow from their cockpit.  What you can end up with is a gordian-knot-conflagration of conflicting cockpits – each struggling to present your design flow to you from its own perspective while “encapsulating” (that’s a code word for “hiding the useful controls in”) the tools from all the other vendors.  In Aldec’s case, they have done a nice job of letting you use the project manager if you need it and skip it if you don’t.  Active-HDL also includes an IP Core generator and testbench generator to round out your creation suite.

When it comes to simulation and verification (which is what the fuss is really all about), Active-HDL includes basically every feature you’d want in a high-end simulator.  Verilog and VHDL are both supported, of course, along with SystemC and SystemVerilog.  The suite also includes code coverage tools that tell you what parts of your design are being exercised by your testbench – including line, statement, branch, expression, and condition coverage. 

The ALINT design rule checker detects design and coding-style problems such as clock and reset issues, simulation and synthesis incompatibilities, and testability issues.  ALINT comes with a large set of rules built-in, and it includes a framework that helps you set up your design rules – letting you create custom rules, manage the checking process, and analyze and debug the results. 

On the strategic marketing front, Aldec has carefully crafted their tools to be closely compatible with existing ModelSim environments.  Scripts, configuration files, and other environmental accouterments can be run as-is directly from ModelSim.  If you price both tools and happen to notice Active-HDL being cheaper, adding Active-HDL licenses into your ModelSim environment should be a hassle-free experience – and that’s just the way marketing wants it.  Keeping a viable alternative at hand is one of the best ways to control a gorilla and to keep him from getting too aggressive and starting to take over.  Aldec’s clever subtlety on this front should be a major competitive “in” for them in a lot of accounts.

If you require industrial-strength verification that spans both the FPGA and ASIC realms, Aldec has a new version of their Riviera-PRO.  Riviera-PRO includes all the neat verification features of Active-HDL (without the design entry stuff) as well as support for assertions (PSL, SVA, and OVA), Verilog Simulation Optimization to accelerate the simulation performance of Verilog designs, and connections to Aldec’s hardware co-simulation solution.  The company has also just announced support for the Open Verification Methodology (OVM) co-authored by Cadence and the Universal Verification Methodology (UVM) from Accellera. 

Aldec has also gotten more aggressive on the OEM front, recently announcing a partnership with Altium to provide the simulation component of Altium Designer.  Aldec is also the supplier of simulation for Lattice Semiconductor’s tool suite.

Aldec is clearly maneuvering to position itself as a deep horizontal supplier of verification technology – competing with broad vertical EDA companies like Mentor Graphics, Cadence, and Synopsys.  On the FPGA side, they are certainly a viable option with a very robust tool suite, and their increasing aggression in the ASIC market should have some trickle-down effects that boost their FPGA offering as well. 

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