CHELMSFORD, Mass. – July 12, 2010 – Mercury Computer Systems, Inc. (NASDAQ: MRCY,
www.mc.com), a trusted ISR subsystems provider, announced the Ensemble™ 6000 6U SBC6521, the first module in a line of Intel®-based, multi-plane-enabled 6U modules. The module was specifically designed and optimized for high-density processing, high memory bandwidth, and I/O in a single OpenVPX™ slot within an ISR subsystem.

Mercury’s innovative OpenVPX multi-plane architecture approach creates an extensible architecture that facilitates interoperability among the various subsystem functions. The expansion plane, one of the planes in the OpenVPX multi-plane architecture, provides scalable I/O and high-speed communications between the SBC6521 and the rest of the subsystem. Scalability and intra-system high-speed communications are crucial elements for the embedded signal and image processing applications required by all ISR subsystems; for example, as part of an ISR subsystem, the SBC6521 supports high-powered XMC mezzanine cards for electronic warfare (EW) applications such as high-speed direction finding and signal jamming.

The SBC6521 module also serves as the subsystem host for the previously announced GPU based Ensemble 6000 Series GSC6200; together these modules form the basis for embedded rugged defense surveillance platforms, performing processing, exploitation, and dissemination (PED). When augmented with Mercury’s the SBC6521 and the GSC6200 products, PED applications can achieve 10-60 times greater performance compared to previous generation systems.

“Mercury’s commitment to our new Intel product line will make our ISR subsystem customers highly successful through the superior performance and performance-per-Watt that Intel processors can offer,” stated Didier Thibaud, Senior Vice President and General Manager of Mercury’s Advanced Computing Solutions Division. “With our new Intel-based product line, we are providing application portability and investment protection through a seamless migration path to Intel technology.”

For more information on Mercury’s 6U OpenVPX product line, visit http://bit.ly/MRCY-Intel-
SBC, or contact Mercury at (866) 627-6951 or info@mc.com.

Mercury Computer Systems, Inc. – Where Challenges Drive Innovation®

Mercury Computer Systems (www.mc.com, NASDAQ: MRCY) is a best of breed provider of open, application-ready, multi-INT subsystems for the ISR market. With 25+ years’ experience in embedded computing, superior domain expertise in radar, EW, EO/IR, C4I, and sonar applications, and more than 300 successful program deployments including Aegis, Global Hawk, and Predator, Mercury’s Services and Systems Integration team leads the industry in partnering with customers to design and integrate system-level solutions that minimize program risk, \ maximize application portability, and accelerate customers’ time to market. Mercury is based in Chelmsford, Massachusetts, and serves customers worldwide through a broad network of direct sales offices, subsidiaries, and distributors.

San Jose, Calif., July 12, 2010—Altera Corporation (NASDAQ: ALTR) today announced it has enhanced its Arria® II GX FPGA variant with 6.375-Gbps transceivers and up to 1.25-Gbps LVDS support, while broadening the reach of the family with the addition of the new Arria II GZ FPGA variant. As a result, the 40-nm Arria II family provides the lowest power 6- Gbps transceiver solutions shipping today, featuring up to 50 percent lower static power over competitive devices.

Many applications commonly implemented in FPGAs are moving to faster transceiver speeds, driven by the need to support mainstream protocol standards such as PCI Express® (PCIe®) Gen2, SATA III, CPRI-6G, Interlaken and RXAUI. In addition, system power consumption is becoming an increasingly challenging design constraint. The new Arria II GX and GZ devices enable designers to solve both challenges.

Arria II GX FPGAs feature up to sixteen 6.375-Gbps transceivers and faster I/Os than the previous generation of Arria II FPGAs, making them ideal for a broad array of applications in markets such as wireless, wireline, test, medical and storage.

With Arria II GZ devices, customers can achieve the power-reduction benefits of the Arria II family across applications with significantly higher bandwidth requirements. The new Arria II GZ FPGAs feature up to twenty-four 6.375-Gbps transceivers, up to 400-MHz DDR3 interfaces and up to 726 I/Os. Furthermore, its processing capacity has been increased to include a PCIe Gen2 hard intellectual property (IP) block, 30 percent more multipliers and 25 percent more user logic than the original Arria II GX family.

“Since their introduction, our Arria II devices have enabled our customers to solve their performance and power challenges and bring truly unique products to market,” said Luanne Schirrmeister, senior director of product marketing at Altera Corporation. “With these extensions to the Arria II family, we are boosting the number of applications that can benefit from the unrivaled capabilities of these devices.”

With protocol reference designs, a new Arria II GX Development Kit, 6G Edition and easily accessible online design resource centers, designers can easily meet the challenges of high speed serial transceiver design with Arria II GX and GZ FPGAs. Altera’s transceiver technology provides easy-to-use signal integrity features that accelerate product development, while consuming less power than competing solutions and quickly resolving transceiver design challenges. The Arria II GX and GZ families feature up to 350K logic elements (LEs) and up to 16.4 Mb of embedded memory. For detailed information on these new devices, see http:// www.altera.com/pr/arriaiigxgz.

Pricing and Availability

Arria II GX FPGAs are shipping now and are supported in the Quartus® II design software version 10.0. Arria II GZ devices will be supported in the Quartus II design software version 10.1 when the device ships in the fourth quarter of this year. Contact your Altera® sales representative for pricing.

About Altera

Altera programmable solutions enable system and semiconductor companies to rapidly and cost-effectively innovate, differentiate and win in their markets. Find out more about Altera’s FPGA, CPLD and ASIC devices at www.altera.com. To subscribe to Altera’s RSS/XML news feeds, visit Altera RSS Feeds.

SAN JOSE, CA and PENANG, MALAYSIA–(Marketwire – July 12, 2010) – The Asia Symposium on Quality Electronic Design (ASQED2010) today announced its final program consisting of several keynote speeches by industry leaders and experts from Synopsys, Texas Instruments, University of Tokyo, Elabs and Silicon Hive, tutorials, and over 70 technical presentations.

This is the 2nd annual ASQED event in Asia. The Conference is being held on August 3-4, 2010 in Penang, Malaysia. ASQED plays a critical role in promoting quality-based electronic design and manufacturing in Asia and is an integral part of establishing a communication link between semiconductor, Nano-Electronic, Bio-Electronic, MEMS/NEMS, PV technologies, and disciplines such as design, manufacturing, test, and packaging.

Powerful Keynotes Headline Conference

The list of plenary keynoters offers a comprehensive perspective from design, process, and tool methodologies. Keynoters and their topics include:

Creating a More Sustainable World through Smarter Design
John Chilton, Senior Vice President, Marketing & Strategic Development, Synopsys

Neuromorphics: The reality of nanoscale devices as part of future System on System (SoS) integration
Prof. Kamran Eshraghian, founder and President, ELabs

Bio-inspired Electronics based on Spin and Dipole Fluctuated System
Dr. Hitoshi Tabata, Professor, Head of Department of Bioengineering, The University of Tokyo

Analog IC Market Trends: The OLD becomes NEW again
Paul Emerson, General Manager, Texas Instruments

Leveraging parallel processing in SoCs
Dr. Jeroen Leijten, Co-Founder and Chief Technology Officer, Silicon Hive

Tutorials

ASQED2010 offers the following tutorials by industry experts:

Terascale Computing and Interconnect Challenges: 3D Stacking Considerations
Dr. Tanay Karnik, Intel

Planar and Nonplanar Structures Thermal Modeling Studies
Dr. Rajiv V. Joshi, Research Scientist, IBM T.J. Watson Research Center

ESD + RFIC Co-Design for Whole-Chip Design Optimization
Prof. Albert Wang, Dept of Electrical Engineering, University of California

IPC Standards and Electronics Manufacturing Environment
David W. Bergman, Vice President, IPC

Technical Sessions

ASQED2010 technical session consists of over 70 presentations by engineers and researchers worldwide, covering the following topics:

• Circuit & System Design
• Test & Verification
• IC Packaging Technology
• PCB and PWB Technology & Manufacturing
• Semiconductor & Nano Technology
• Bio Electronics Innovations
• Photovoltaic Technology & Manufacturing
• Electronic Design Automation Methodologies
• Micro-Electro-Mechanical System (MEMS)

Papers will be presented in three parallel tracks on Tuesday, Aug. 3rd and Wednesday, Aug. 4th.

Sponsors, Supporters and Exhibits

ASQED2010 corporate sponsors and supporters include Synopsys (Titanium Sponsor), Cadence Design Systems, Silterra and NIMOS. ASQED also includes company exhibits.

About ISQED

ASQED2010 is the second event in Asia organized by the International Society for Quality Electronic Design (ISQED). ASQED2010 is co-organized with the Malaysian Industry Government Group for High Technology (MIGHT) and the Malaysian Institute of Microsystems (MIMs) with support from the Malaysian Industrial Development Authority (MIDA). Conference proceedings will be published by IEEE and posted in the IEEE digital library.

Please refer to the conference website at http://www.asqed.com for further information about the conference.