Axiom 1: No matter what we’re doing, something else seems like a better idea. In many cases this takes us forward in a circuitous semi-linear manner towards something new. We may get there by precise navigation, or, more typically, we arrive in a Brownian random-walk kind of mode – after which we can claim credit for great prescience.
Axiom 2: We have short memories. We look forward, not backward. No wasting time on “been there, done that” when we can focus on “wanna go there, wanna do that.” (Or more succinctly expressed in the modern vernacular simply as “Want!”)
Axiom 3: One leg is shorter than the other. This means that, without suitable points of reference, we tend to walk in circles.
Theorem: Policies and ideas tend to move in circles, moving from one idea to its opposite and back. Why? By Axiom 3, we tend to go in circles; we don’t notice it since, due to Axiom 2, we don’t really pay attention to where we’ve been, and so we have no points of reference to alert us to the fact that we’ve already been there before. And we never stay still since, no matter where we are, Axiom 1 says there’s always another better place to go. It just so happens that, for lack of other choices, that may, by necessity, be someplace we’ve already been. Which is always better than where we are, even though we’re where we are because where we are was better than where we were when we were there.
Call it the Dory effect. Somehow where we’ve been before seems new.
Case in point: semiconductor vertical integration, or the lack thereof.
Back in the day, when you wanted to make a chip, you had to have a way to make it. The procedure consisted of implementing an idea in circuitry that was tuned to the characteristics of your fab. Which you had to have. If you were a real man. (And, if you can imagine this, the industry was even more solidly male then than it is today. And it’s pretty damn male today… come on folks, let’s mix it up a bit!)
Typically, you would target a process you had in house, make sure that there was sufficient capacity in the fab to satisfy the marketing projections (or whatever derating you placed on the marketing projections) and that the process itself would have a lifetime sufficient to satisfy the projected product lifecycle. And that it would meet the cost requirements for commercial success.
Of course, some companies failed by starting on one technology, and then, right when it was about ready to release, realizing a new technology was just around the corner that would work way better. “Let’s don’t release the old stuff; we need new stuff. We’ll simply migrate the existing design to the new technology and then release it. How hard can it be?” However, as such companies could typically be characterized as what paleontologists would call evolutionary dead-ends, such behavior tended to be self-limiting.
And then, somewhere along the way, fabs got awful damn expensive. The cost of construction migrated from $M to $B, and people started thinking real hard about how important it was to have a fab. And the industry horizontalized: companies were grouped into “fabless” semiconductor companies and foundries. With the exception of a few large companies, which, instead of simply being called “semiconductor companies,” as would have been natural in the past, were now given a special name, the “integrated device manufacturer”, or IDM. The rule had become the exception.
So now the industry was mostly layered: a design layer focused on chip functionality and a fabrication layer focused on physical realization. At the interface was the realm of the PDK, whereby the requirements of the fab layer could be communicated to the design layer. And tape-out was the means whereby the results of the design layer were communicated to the fab layer (for further acceptance testing by the fab).
And that’s more or less a tremendously simplified picture of where we stand today. But things are changing.
The nice segmentation between design and fab has been gradually eroding. More and more information is trickling across the interface from fab to design; it’s simply harder and harder to do a design without knowing in growing detail the intricacies of the physical implementation. Looked at another way, it’s becoming harder and harder to decide whether the layout process is a design-layer or a fab-layer activity.
Fabs have always abstracted their details to some degree. At the very least, a single transistor is an abstraction of diffusions and depositions that can be encapsulated in a single set of equations that define the operation of the device. And for years we’ve had gates and other “standard cells” that further abstract the collection of transistors and other components. All to facilitate their modular interconnection in a manner that has a high likelihood of behaving as desired.
None of this, so far, is news. But such developments have an insidious way of drifting imperceptibly, much in the way an inebriated air-mattress lounger gets caught up in a rip tide and groggily lifts his head at some point when he notices that the seagulls aren’t as loud as they seemed before and beholds the shore far off in the distance.
At DAC this year, TSMC talked about a couple of developments that, in and of themselves, are mere incremental natural developments from today’s way of doing things. First, they’re trying to approximate something akin to standard cells for analog circuitry. Maybe not quite the same thing, but larger analog blocks that have some dials that can be adjusted and can at least give designers a head start on the design, with greater predictability of performance, power, and area.
And those represent the other, broader shift. TSMC is making a much bigger deal about performance, power, and area – PPA. Given all of the subtle, complex interactions and variability at 28 nm and below, the level of abstraction must grow, not only to support modularity and design efficiency, but also to get a handle on the increasingly difficult problem of satisfying the performance, power, and area requirements of a chip. The harder it is to predict and manage these parameters, the more circuitry you want to pack into a single well-characterized module.
It seems innocent enough; physical IP is nothing new. It’s just that TSMC in particular seems to be willing to provide more and more of it. And with the emphasis on SoCs, you could project forward to a world of embedded systems designers assembling foundry-provided blocks on a chip much in the way traditional embedded systems designers have historically assembled them on a PC board. Project it a bit further, and TSMC could be doing this itself.
And there’s no reason to think that this would be limited to TSMC. Were the availability of such modules to be increasingly viewed as a service provided by the foundry, other foundries would need to operate in a similar manner.
In other words, at some point, there would no longer be any segmentation between design and fabrication. We would be back to the world of semiconductor companies handling both concept and realization. Now, in a typical “what’s old is new model,” you might have seen this coming – but the more predictable outcome would be the “fabless” guys deciding they didn’t have enough control of their fabs and buying them back. But in the scenario that seems to be playing out, it’s actually the fab guys that would be more likely to buy the design houses, building from the bottom up.
Which would bring us full circle. Although, of course, not quite. It’s not like a circle spinning in one place; it’s like a circle spinning as the center moves along a path (either semi-linear or semi-Brownian). And a point on that circle will trace something like a cycloid, although since the reference point is the center of the circle, the motion will occasionally appear retrograde. We go backwards. And yet we go forwards.
We may be approaching where we were, but we’re doing so from a different direction. And our legs are almost the same length, so we don’t notice the arc we trace. And so, like Dory, we re-occupy a familiar space with breathless novelty. And in so doing, we satisfy all three axioms and prove the theorem.
QED.
