It used to be simple – you designed your chip, converted the gates to a standard interchange format like GDS, taped out by actually writing to big reels of magnetic tape, and threw the reels at the chip maker. A few weeks later the wafers came back. If you were happy to pay a few more tens of thousands of dollars, then you could send copies of the tape to another chip manufacturer to get continuity of supply and to play the competitive pricing game. (OK – the step labelled “design your chip” was, even in the good old days, a slightly more complex step than “first catch your hare.”)
But this is no longer the case.
Moore’s law has continued its remorseless march of making device geometry smaller, with the result that chips include many more functions and have become much more complex. At the same time, meeting the requirements of the manufacturing process has become more and more demanding. It is no longer enough to run the layout through a Design for Manufacturing tool before tape out. Instead, even tools at the ESL or architecture planning level need to know details about your target process. Only a little further down the design chain and you are totally dependent on the final process.
This has multiple consequences. The designer, once having made the process decision, can no longer change his mind. If he does, he will incur some serious time penalties. And the EDA companies supplying the tool chain have to provide multiple options at many links in the chain, each tuned to a specific process, specified by the rules provided by the foundries as Process Development Kits (PDKs). And it is not as though each process node for each foundry has a unique PDK: TSMC’s 28nm process will have at least four versions, and each version will require its own PDK. (One EDA company suggests, however, that 80% of designs are manufactured in only 20% of the available processes.)
At the same time, the EDA industry is struggling to be profitable, despite list pricing that makes one’s eyes water. The extra cost of recouping the investment in all these different variants will have to be borne by charging someone money at some stage.
Since tools are becoming so foundry specific, perhaps the route will be to return to the proprietary tools model of some thirty years ago, and of today’s FPGA companies. Here the design tools are provided by the foundry and, effectively, given to the developers, although in reality, the developers will pay for the tools with a few extra cents in die purchase cost. Obviously the foundries will need to have good quality tools to give to the designers, but this could be easily managed by buying one of the EDA companies. For example, the stock markets think that the leading foundry, TSMC, is worth over $50 billion. (This on turnover of around $9 billion last year – and predicting around $12 billion this year.) By comparison, Cadence last year turned over $843 million, and the market values it at around $2 billion. For around $2.5 billion dollars, TSMC could buy Cadence – Synopsys would be slightly more expensive and Mentor would be slightly less so. In all cases there would be non-core businesses within the EDA companies, such as PCB design, that might be sold off to reduce the cost.
If this happened, what would be the effect on users of the design tools? Probably they would see very little difference. As previously argued, they will already have chosen the technology, and possibly the tools they will be using might be even better tuned to the process. Few of the EDA companies have introduced innovation in the last few years – most innovation in EDA has come from small start-ups who have then been bought out by the bigger companies. And there would be no reason why this process should not continue, since bright ideas to improve aspects of the design chain will not suddenly stop.
In the embedded systems industry, a similar process is already taking place: Intel has recently bought Wind River, a supplier of operating systems, middleware and development tools, and ARM bought Keil, another embedded tools company, some years ago.
I had more or less got to this point in developing this article when Cadence decided to up its game and launched the EDA360 programme.
EDA360 is aimed at catapulting EDA to a new level. “We want to move EDA sales from $5 billion to $25 billion,” said Cadence’s evangelical chief marketing officer, John Bruggeman. Cadence is positioning EDA360 as a cross-industry programme and is looking forward to the response from other companies.
The thinking behind EDA360 is that, increasingly, SoCs are as much about software as they are about hardware, and today the software development for an SoC usually lags behind the hardware development, in part because the SoC users are responsible for most, if not all, of the software. Since they want to differentiate their products through applications, users are increasingly going to expect that their SoC is supplied ready with all the software needed for them just to load up their applications. For example, SoCs will need USB 3.0, but customers don’t want to have to learn about USB 3.0; instead they want the hardware within the chip and the software stack to come integrated and fully conformance-tested. This will cut down on the work they need to do and accelerate the speed with which they can get their product into the market.
This means that the silicon companies will have to spend considerably more effort on software, and, to meet this need, instead of just shipping hardware design tools, the EDA companies will need to provide the silicon design companies with a chain of software tools, fully integrated with the hardware tools, not just for hardware/software co-design, but for emulation and verification as well.
At the same time as launching the EDA360 initiative, Cadence has begun the roll-out of a whole series of company announcements, which show that the company is prepared to match their ideas with actions. The first release announced a partnership with Wind River, which will mean that the Simics system simulator will run alongside the Cadence development chain. (Simics was developed by Swedish company Virtutech, acquired by Intel in February this year and rolled into the Wind River portfolio.)
Also announced was the Verification Computing Platform, a new high performance verification machine. Billed as an environment for emulation, simulation, verification, and acceleration, the Palladium XP will model up to 2 billion gates, run at up to 4MHz, and can support up to 512 simultaneous users. The photographs with the release made it look like a desk-top machine: in the flesh it is about the size of two three-drawer filing cabinets standing side by side.
A week later, introducing EDA360 to Europe, Cadence continued to roll out announcements, including what they are calling the Cadence Open Integration Platform. (These platforms get in everywhere.) This includes integration-optimized IP, the new Cadence Integration Design Environment (IDE – funny, I thought that meant something else in the development world), and integration services.
While ASIC and SoC designers are increasingly using IP, integrating IP into a design is a long way from simple plug and play: there are significant problems integrating the IP, and there are issues with developing software and drivers for it. Cadence is assembling IP partners, and the first members are GDA, IBM, RapidBridge, and Sonics. Working with them, Cadence will offer packages of integration-optimized IP. The example they give is USB 3.0, complete with drivers, conformance-tested and silicon proven. With Sonics in the party, they are also offering a straightforward way to hook the IP together. The IP will be listed on ChipEstimate.
This whole approach is interesting and likely to improve Cadence sales. After all, the IBM360 range of computers was a market success and changed the model of computing for at least a generation. But is EDA360 going to increase Cadence revenue five-fold, as Bruggeman insisted that the industry needs to do? That is a really ambitious target, and even if it were merely rhetorical, it still suggests that there are underlying hard targets. Let us assume that this program doubles all EDA companies’ revenues in the next two years. TSMC and the other foundries are also expecting significant growth. Cadence and the other EDA companies are still going to remain small by comparison and vulnerable to take-over. In fact, if EDA360 works, they will be even more attractive to the foundries. I see the foundry-specific tool-chain as inevitable: come back in two years’ time and prove me wrong.