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Mixing it Right for Mixed Signal

Clearly there is a real and growing demand for mixed-signal devices.  Technology advances are ensuring high-performance analog-rich designs can be fabricated more cost effectively.  The inexorable shift to smaller geometries on standard digital CMOS processes has encouraged more foundries to exploit still-viable, larger nodes for mixed-signal processes.  Meanwhile, other foundries, entirely focused on mixed-signal, are developing new BiCMOS, RF CMOS and SiGe processes.  Production capacity and process choice for mixed signal devices is increasing to meet growing demand.  Variations for low power, low voltage, high voltage and high frequency provide plenty of choice for the discerning mixed signal device designerThere is even growing interest in SOI (silicon on insulator) processes, providing yet further options for higher performance or lower power. (See sidebar: Process choice)

While increased choice can only be good, designers need to take care selecting the best process and technology for a specific application. From a performance perspective, as multimedia functions drive the communications and consumer convergence, the need for speed is generating new interest in the more exotic processes, such as SiGe.  Yet the demand for increased functionality without increasing chip area or cost edges you towards ever smaller CMOS process geometries.  Increased integration, particularly of RF and analog circuitry, as well as, more recently, MEMS-based devices, favors mixed signal, BiCMOS and RF CMOS processes.  Low-power design, whether the focus is on active or standby power, throws a curve ball into the conflict.

If cost is critical (and it nearly always is), clearly the more advanced technology nodes are more expensive, especially at first.  But note that exorbitant mask and NRE costs can be offset by higher yields and lower per-chip costs, as long as volumes are high enough.  Similarly, design shrinks can extend the life (and profit) of existing high-volume SoCs and their derivativesFeature-rich technologies such as SiGe offer considerable performance advantages for mixed-signal devices, with speeds comparable to that provided by RF CMOS at smaller process nodes, without the need to migrate, or before the RF options at those nodes are available.

Figure 1 – SOI wafer

Time to market considerations include assessing the skills gap and learning curve associated with migrating to new process nodes or technologies.  But coming to market at the right time is ineffective if you have the wrong product at the wrong price point.

How much Analog?

One of the first questions to ask is how much analog circuitry needs to be on the chip.  The pressure to reduce chip count, integrating as much circuitry as possible into a single device, comes from the price and form factor constraints associated mainly with portable (largely, but not entirely) consumer products.  There is an argument that maximizing digital signal processing can minimize the amount of analog circuitry needed.  While the relative performance merits of such an argument are beyond the scope of this article, the designer should bear in mind that an all-digital implementation might make a digitally-oriented CMOS process, rather than an all-out mixed-signal process, the optimal solution.  Consider also that, when the digital portion of a design dominates, moving to a smaller geometry results in significantly greater die area reduction and performance improvements as well as cost and yield advantages.  Beware, however: analog circuitry does not migrate in the same way as digital. The reason for this is that analog circuits are always dominated by passive components that do not scale with lithography changes.  In addition, at 90 nm and below, analog performance begins to degrade.

If, however, the design requires the technology advantages that only analog signal processing can bring, and if the integration of analog, RF and MEMS devices is essential, then the choice has to be a BiCMOS or RF process.  It is certainly worth evaluating which process node is optimum, since it may not be necessary to move to a smaller geometry, especially as analog does not scale so well and may not give you the smaller die size you need to reduce per chip costs.  As a general rule of thumb, if your design is 60% analog and 40% digital, you probably should be thinking of around a 0.35-µm process, but if it is closer to 80% digital and 20% analog, then 0.18 µm may prove a more optimal choice.

Figure 2 – A 60 GHz PA in SiGe BiCMOS

Two customer examples spring to mind.  The first is a straight Bluetooth transceiver chip for mobile phone handsets.  Low cost was a key constraint.  Digital circuitry was minimal, and the design was fabricated on a 0.35-µm CMOS process.  It won out dramatically on price compared to slightly higher performing, but higher priced, competitors.  At that time, targeting the next process node would only add cost, while the marginally smaller die size and increased performance proved not to be important to the customer.  Now, however, as chipsets evolve, the customer is working on a new design to add a whole host of digital processing options for the Bluetooth module, such as ultra low power, Wibree, Zigbee, WiFi and NFC/RFID compatibility.  The digital/analog balance has changed dramatically.  Now 90- to 65-nm RF CMOS processes fit the bill to deliver the density and performance at the best cost.

Another customer in the mobile broadcast market was designing a software-defined radio companion chip for a broadcast receiver chipset supporting multiple digital and analog standards.  Digital content of this mixed signal device was higher than the first generation part, and the company had to move up from 0.25 µm to gain the price advantage it needed to compete successfully.  The choice of a 0.18-µm RF CMOS process ensured the design met the performance specification at the right price point.  The attraction of better performance and an even smaller die size with a 0.13-µm geometry was strongly resisted (along with higher mask costs and risk).  The key message here is that, providing the design meets the specification, there is no need to over-specify – ‘just good enough’ will give you the optimal price-vs.-performance trade-off.

Of course, there will be times when only the best is good enough.  In the fast growing 40-GHz wireline and optical communications market, for example, the only option is the highest performing processes in the most advanced, fifth-generation nodes, typically 0.13-µm SiGe BiCMOS.  Such decisions are clear cut.  More difficult is choosing between technologies and process nodes for not quite so high performance applications.

Interestingly, with the shrinking of SiGe BiCMOS mixed signal processes, now down to 0.13 µm, circuit speed increases significantly, typically two process nodes ahead of RF CMOS. For example, 0.35-µm SiGe BiCMOS is equivalent to 0.18-µm RF CMOS, and 0.13-µm SiGe BiCMOS is equivalent to 65-nm RF CMOS. Analog experts will need to study the importance of other key differences in characteristics between the transistor styles and processes, especially concerning gain, matching, low- and high-frequency noise, and ESD protection.

Figure 3 – Typical fT by process node

Process Choice:

Standard CMOS: Lowest cost, but minimal analog functionality.  Good scalability for high-density digital circuitry.

RF CMOS: Additional process steps/design rules to support analog devices such as high-resolution poly for resistors, inter-layer dielectrics for MiM capacitors, and thick metal for inductors.  Does not scale so well if high percentage of analog content.  Scaling beyond 90 nm might degrade analog performance. SOI versions also available with the inherent advantages of lower leakage and protection against single event upset, such as latch up.

BiCMOS: Better performance than RF CMOS by using high-frequency bipolar transistors. Intended for high-performance analog applications.

SiGe BiCMOS: Highest performance, ideal for high-speed optical or radar applications.  Good scalability, low leakage.  Highest cost, although lower-cost, lower-performance options are available that still offer significant performance advantages over RF CMOS of a similar geometry.

Technology Trade-Offs – Top tips

Performance: Stick to ‘just good enough’ performance – don’t be tempted to over-specify if price is important.  If you need speed, you can’t beat SiGe BiCMOS.

Geometry: Moving to a smaller feature size allows increased circuit density, higher performance, lower power and reduced die size.  Yields will increase with smaller die and/or larger wafers.  Mask and NRE costs will increase, but if volumes are high, per-chip costs will reduce.

Scalability: In CMOS or BiCMOS, analog circuitry does not scale in the same way as digital.  Designs with mostly digital content will benefit most from process shrinks. 

Low power:  Low-power processes are best for low active power in ‘always on’ devices.  High leakage in standby or power-off modes can be a disaster for the power budget in some applications.

Costs: Mask costs increase dramatically with each process node.  BiCMOS and RF CMOS process masks cost about 20% more than standard CMOS; SiGe can be more than twice as much – but then, so is performance.

Standing by or always on?

Low power design is a predominant trend today, both to prolong battery life for portable products and to meet ‘green’ energy saving initiatives.  Optimized low-power processes are currently offered by most foundries.  But it is important to distinguish in your design between active and standby power consumption, and to determine whether the end product is going to be operating mostly in an ‘always on’ environment, like the mobile phone, or mainly on standby with short bursts of activity, such as in some wireless sensor networks.  Low power processes might be ideal for the former, but high leakage makes them unsuitable for many applications, and particularly at 90 nm and beyond.  General purpose processes, and SOI are the better choices here.

A further consideration for applications in the automotive, transport, military, medical and industrial sectors is the need to interface to high-voltage power supplies.  Some foundries offer processes that support high-voltage operation, which can be integrated in SoC and ASIC designs, offering high-density circuitry on a 0.18-µm geometry.

Providing a service

Last, but not least, the choice of foundry plays an important role in the process decision.  The ‘best known’ may not always have the best choice or the most innovative of processes.  Sometimes a reputable specialist may be more accessible or supportive, particularly for occasional customers. If your volumes are not huge, then look for a foundry that offers multi-project wafer (MPW) runs.  MPWs provide a low-cost, low-risk entry to SoC and ASIC design.  They can offer not only prototype and qualification volumes, but they can also deliver several hundreds of parts using short wafer runs.  MPWs delivering say, 50 chips, can even be competitive with FPGAs for prototyping, plus they provide a far more realistic at-speed prototype environment for early software development and system qualification applications.

For mixed-signal designs especially, foundry choice should also consider the technical support available for design rules, process models, front-end support, access to external libraries, information on process characterization and a migration path to the next-generation technology.  Keep in mind that a third-party service provider can greatly facilitate access to process, technology and schedule information, as well as provide technical support.

A key part of any foundry deliverable is the process design kit (PDK) which includes device models, schematic and layout libraries, and verification decks. In particular, the quality of the analog/RF models can vary greatly from one foundry to the next, so special attention needs to be paid to this aspect in choosing your foundry partner. Poor-quality models can lead to differences between simulation and measured results, resulting in the need for further iterations of the design. These risks can be further reduced with the running of corner lots in the fab, simulating the best and worst case process spread that could be possible with mainstream production lots.


Author Profile


Wes Hansford is Deputy Director with Mosis, a US-based independent service provider with access to the fabrication of MPWs, prototype and low volume production quantities of analog and mixed signal ICs.  It has a wide range of innovative processes from AMIS, AMS IBM and TSMC.  See: www.mosis.com

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