Bonnnngggg…

Two thousand and seven creeps quietly toward a dignified death, trailing tales of victory and woe in the vast vortex of its widening wake.

Bonnnngggg…

Two thousand and eight eases expectantly into view, its perils and possibilities awaiting their unwitting victims and victors with equal voracity.

Bonnnngggg…

Mister Moore is a maddening mistress.

Naught seven was a year of hunker down and deliver.  In terms of new product announcements in the FPGA sphere, it was a year of bolster and boost, respond and reinforce.  Since it was an odd-numbered year, we didn’t have major Moore’s Law announcements – you know, the ones where the FPGA companies say “Announcing the new XYZ-nanometer Razmatazz FPGAs – Faster, Cheaper, and with Lower Power than anything ever produced, with new Secret Sauce features that we hope our competitors don’t have when they launch their XYZ-based devices” and with fine print that tells you we’re just kidding for this year, and you can expect volume shipments of this family in a year or more after we’ve figured out how to actually build the things.

Instead, we talked about variations on a theme – families that were announced in 2006 are “now shipping in volume,” and we’re adding new IP, software support, ecosystem partners, and development boards that make them useful for real design work.  Companies worked to deliver on the promises made in 2006.  Of course, nobody did what they expected.  That’s the nature of high-tech engineering and marketing.  Some fared better in business and others made substantial technology progress without the revenue rewards to show for it. 

Next year, we’ll likely be back on the speculative execution side of things.  FPGA companies will play press-release chicken… waiting as long as possible to announce new product lines while still trying to be “first” – even though the distinction matters mostly in the board room and the company all-hands meeting.  Quick — who remembers which announced first between high-end 90nm Stratix II, Virtex 4, and Lattice SC?  Now, out of those of you that remember, who actually cares?  Not many hands left, huh?

Designs that we did in 2006 and 2007 will actually start shipping in volume.  FPGA companies will rejoice while recognizing revenue they really earned two years ago when they convinced us to populate our prototype sockets with silicon still more envisioned than enabled.  We trusted and, after a time, they delivered and we succeeded and the purchasing public can now enjoy the fruits of our joint labors. 

Semiconductor companies live in a strange time-warped world where the rewards lag performance by an amount that de-couples cause and effect.  One product team will develop something truly outstanding during a time when revenues are bad or even declining.  As a result, company morale may be low, downsizing may even be in progress, and the remarkable engineering accomplishment may go almost unnoticed.  Two years later, the silicon that resulted from that project may be designed into products that hit their high-volume strides, margins are great, big orders are streaming in, and the boom times begin — all on the backs of an engineering team that might have long since dissipated in disappointment.  This is the reality of engineering in our industry.  If you don’t understand that or can’t cope with that mode of working, you might best look for another occupation in 2008. 

Early this year, a few new chip families did show up on our radar – Lattice rolled out its “Freedom Chip” program – a cost-reduction strategy to compete with Xilinx’s Easypath and Altera’s decidedly more robust HardCopy.  Xilinx launched Spartan 3AN – a stacked-die solution that acts like a non-volatile FPGA if you aren’t too picky about semantics.  They were apparently targeting the folks that would go for Actel’s flash-based families, Lattice’s XP family, or even Altera’s Max II CPLDs.  On the structured ASIC front, ChipX brought us embedded arrays – something between a structured ASIC and a standard cell.

March opened with a bang as Altera rolled out Cyclone III – the first low-cost family on the 65nm process node.  (See, at least WE noticed who announced first.  Of course, in a year or two those details will probably be long forgotten.)  This has given Altera a few months of uncontested low-end superiority and a selling spree with the usual cost/density, speed, and power advantages that come with a new process node.  On the high end, however, Xilinx has the upper hand, shipping their Virtex-5 devices well ahead of Altera’s Stratix III schedule.  Xilinx worked to retain some of the low-end design-ins with a DSP-specific version of their 90nm Spartan-3 family.

In May, Lattice launched the second generation of its non-volatile flash/SRAM hybrid XP family – dubbed XP2.  At almost the same time, Altera responded to Lattice’s low-cost serdes-having strategy with Arria GX – a low(ish)-cost FPGA family with its own built-in serdes transceivers.  Over the next couple of years, we look for transceivers to become more mainstream across all levels of programmable logic as standards like PCI Express, Gigabit Ethernet, and others become must-haves.

By September, we were focused on embedded systems on programmable devices as Actel announced they were supporting the new ARM Cortex M1 FPGA-specific processor core with their ultra-low-power Igloo flash-based FPGA family.  The same month, Altera and ARM announced that design-kit support was available for Cortex M1 in Altera devices as well.  Cortex M1 brings an interesting angle to the FPGA-based system-on-chip game.  While it may not have the speed/area/cost specs of vendor-specific processor architectures, it brings a level of standardization that transcends vendor lines and also legitimizes the idea of systems on programmable chips.  At the same time, it makes mountains of existing software and tools viable for use in FPGA-based systems.

The final family of the year is apparently Altera’s Max IIZ – announced just last week.  While masquerading as a CPLD, we all know that Max II is really an FPGA family – in much the same mold as Actel’s smaller flash-based devices, Lattice’s XP and XP2 families, and even now Xilinx’s Spartan 3AN.  The new thing here was that Altera conquered the static power “tell” that belied its true identity.  Now, with static power more in line with CPLD expectations, we can all go back to pretending it isn’t an FPGA.

The last half of the year brought big announcements in the design tool space as well.  Altium rolled out a major upgrade to its increasingly-popular Altium Designer software.  Mentor upgraded its Precision Synthesis suite and also took its ESL-dominating Catapult C Synthesis technology firmly into the FPGA space by cooperating with Altera on an optimized library and design flow from C to FPGA hardware.  Synplicity announced a significant upgrade to their FPGA synthesis tools, as well as acquiring HARDI – a supplier of FPGA-based ASIC verification boards.  Combined with their “Total Recall” technology and their “Certify” prototyping software, Synplicity is now well positioned in the FPGA-based ASIC verification market.

Here at FPGA Journal, we chronicled and commented on these and other developments.  It has been a wonderful year for us as our reader responses and subscriber rates have been at an all-time high.  Next year, we’re excited that another member of our Techfocus Media family will launch – IC Design and Verification Journal will be joining FPGA Journal and Embedded Technology Journal in January.  The new publication will be covering the high-end EDA, ASIC, and IC design space.  We’ll also be welcoming new editors to the team and delivering improved coverage across the board in FPGA, Structured ASIC, Embedded systems, and ASIC/SoC. 

As 2007 comes to a close, we’d like to thank you, our loyal readers, for continuing to give us your time, your interest, and your feedback.  Of course, without you, we wouldn’t exist.  We are here to make your work easier, more productive, more interesting, more relevant, and more fun.  If there are ways we can do those things even better, we’d like to know.