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Tooling up for 65nm

Xilinx Updates Software for Virtex-5

Every time FPGAs hit a new process generation, there is a buzz. People want to hear about the underlying architecture, learn how fast the new devices will go, guess at how much logic they’ll hold, speculate on whether we’ll need a small nuclear power plant to operate them, and marvel at marketing’s ability to take something already quite impressive and exaggerate it to the point where we have no idea what it can actually do. We tingle with excitement. We wait a year until actual devices are available. Then, when the magic moment comes and we get our much anticipated first look at the parts, they look like a little square of plastic and metal just like all the parts we’ve seen for the past twenty years. The logo is updated, but all the extremely cool stuff is otherwise completely obscured. This is where FPGAs don’t offer the same opportunity for nerdly worship that, say, drag racers do. With most other technologies, the cool stuff is right out where you can see it – in all its chrome-plated, titanium-tinted, carbon-fiber-reinforced glory.

In FPGAs, our first (and often only) opportunity to get inside and kick the tires of a new FPGA family is when the software is available. During our use of any FPGA technology, 99% of our interaction with the product as designers will actually be with the software tools and not with the devices at all. Those exotic chips will sit there on the lab bench soldered to our development boards looking basically square and boring.

A few weeks ago, Xilinx announced the world’s first 65nm FPGAs – Virtex-5. Instead of having to wait a year to see them, I got to see one right away. Evidently, Xilinx has had them in select customers’ hands for a few months now, and they actually physically exist. My hands almost trembled as I held the development board. OK, not really. Still, there it was looking just like all the other Virtex parts, only with a 5 tattooed on the top (all part of a smart new logo, of course). Now, however, the software is out and we can all take a serious (albeit virtual) look at the new line.

As we said in our Virtex-5 rollout article, the new family has a 6-input LUT structure. According to Xilinx’s materials, with the combination of the 65nm geometry, the 6-input LUT logic level reduction, and improvements to the synthesis and place and route software, a net gain averaging 30% over Virtex-4 has been achieved. Will your mileage vary? Definitely. FPGA vendors measure performance by running a large suite of known designs through the software for two scenarios under test (like, say, Virtex-4 with ISE 8.1i and Virtex-5 with ISE 8.2i) and comparing results. If the change being measured is a software-only change, such as a synthesis algorithm or placement strategy alteration, we expect to see some designs get worse and some designs get better. If we do some statistics on the results deltas across the entire suite, we can see if the change was a net improvement on average, and if we look at the distribution across the suite we can understand the chances that any particular design will get better or worse.

If the change we’re measuring is a process node jump, however, we typically expect every design to improve by a fairly static amount. In Xilinx’s graph below, we see improvements ranging from zero to almost sixty percent on a suite of 75 designs, with an average of thirty percent improvement. If we were seeing a graph of just the effects of 65nm technology versus 90nm technology, we’d expect a more horizontal line showing roughly linear improvement by reduction in delay numbers, with perturbations caused by less predictable changes in routing delay on the new technology. In this graph, however, we have to guess that the architecture changes from LUT-4 to LUT-6, routing architecture changes (with the advent of new, diagonally symmetric routing), and software algorithm changes are also playing a significant factor in the overall results, making some designs shine while others merely glow.


Graph courtesy of Xilinx, based on a suite of 74 customer designs.

Many serious design teams use primarily third-party synthesis tools such as those available from Synplicity, Mentor Graphics, and, more recently, Magma. The choice of synthesis and physical synthesis tools also throws a large perturbation into the results curve as different synthesis tools excel on different design styles. As we’ve mentioned before, running more than one synthesis tool and comparing results is the best way to assure that you’re getting the most out of your design if performance is paramount.

Xilinx also has worked on the usability of the ISE suite with this release, continuing with features like Xplorer that automates timing closure by iterating synthesis and place-and-route runs on your design with varying tuning parameters and picking the combination that gives the best results. If you’re trying to optimize timing, you can set up a run, go home for the weekend, and come back to find out that the software has automatically tried all the knobs and dials for you. Xilinx claims that Xplorer will give a 10% average improvement over a straight, default run of the tools. Yes, here too your mileage will vary. Performance prediction is a probability game.

The new ISE also boasts better cross-probing and more cross-tool integration, producing a friendlier environment for managing the plethora of programs involved in complex FPGA design today. Floorplanning, constraint editing, timing analysis, and PACE (Pinout and Area Constraints Editor) are all now integrated into the ISE cockpit in order to facilitate more seamless design operation and to enable capabilities like cross-probing between views. Since the software is your primary window into the FPGA (unless you’ve got superpowers that allow you to peek past that big metal square), improvements to the smoothness of the navigation are bound to be well received.

As FPGAs plunge down toward single-digit nanometer numbers, power is a growing concern in FPGA design. With 8.2i, Xilinx is rolling out a complete new suite of power estimating tools to help us understand the power problems in our designs. The new Xpower estimator lets you specify your power constraints and analyze your design’s power consumption at a detailed level in a spreadsheet-like environment. Xilinx is making the Xpower tool available as a free download, separate from ISE.

Because signal integrity is also a growing concern for board designers incorporating FPGAs onto complex, high speed PCBs, Xilinx has also attacked the pinout and packaging arena with Virtex-5 and ISE 8.2i, providing an improved “sparse chevron” pinout structure and adding additional model support for third party PCB tools.

Xilinx’s new ISE 8.2i is available now, so you can go out and take Virtex-5 for a test drive even without waiting for development boards to arrive at your doorstep. FPGA vendor-supplied tool suites are unbelievably affordable and represent one of the most irrationally-excellent values in design automation software today. If you’re considering using any FPGA family, it pays to download or purchase the vendor’s tools to try out your design before committing to a device selection. The tools will give much more dependable results for your particular circumstances than you can possibly get trying to sort through marketing claims and datasheets.

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