feature article
Subscribe Now

High-Density FPGA-to-ASIC Conversions using Structured ASIC: Fills the Gap


Managing the increasing complexity of today’s digital applications calls for new design strategies. Risk, cost and time-to-market (TTM) can make or break a product development. While many designers are turning to FPGAs to reduce risk and improve TTM, the staggering per unit cost of high-density FPGAs quickly becomes intolerable for even low volume applications. Cell-based ASIC solutions offer much lower per unit cost, but the NREs for deep sub-micron technologies are becoming cost prohibitive. Structured ASICs fill the gap by offering excellent per unit cost and reasonable NREs. This paper describes a design flow starting with FPGA prototyping followed by conversion to a structured ASIC. The paper then describes how structured ASICs can be used to support a range of applications and how they can be used to quickly introduce cost effective, complex, digital products to market with minimal risk.

1. Comparing The Different Hardware Platforms

When selecting a hardware platform, the designer has many different options for complex digital designs including field programmable gate array (FPGA), cell-based application specific integrated circuit (ASIC), application specific standard product (ASSP) and structured ASIC technology.

FPGAs provide the quickest TTM due to their quick verification cycles and zero fabrication time. FPGAs also have very low non-recurring engineering (NRE) cost and induce less risk into the development plan than any other platform. On the other hand, FPGAs can have staggeringly high per-unit costs, with top-of-the-line FPGAs exceeding $1000 per part. Thus FPGA per-unit cost can be prohibitive for even relatively low volume applications of five to ten thousand units per year. In addition to cost, FPGAs consume considerably more power than the other options, offer less capacity, slower performance and are susceptible to soft errors and piracy.

Cell-based ASICs offer the best capacity, performance, power conservation and lowest per-unit cost of all the options discussed. However, technical advancements in shrinking geometries have driven reticle costs through the roof. This exponential increase in reticle cost translates to excessive NRE cost, making cell-based ASIC platforms too expensive for all but the highest volume applications. Cell-based ASICs only make sense for applications that require “bleeding edge” performance and have production volumes in the hundreds of thousands of units per year.

ASSPs provide quick TTM since the part is already designed and just has to be integrated by the application design team. They have zero NRE and equivalent performance and power characteristics to cell-based ASIC designs. Per-unit cost for ASSPs are all over the spectrum, from close to what a cell-based ASIC would cost to more than the most advanced FPGA, depending on complexity and market demand. The biggest limitation of using ASSPs is finding one that will implement the function required for the application.

Structured ASICs fill the gap between FPGAs and cell-based ASICs. They can be developed in less than half the time and 30% of the NRE for a cell-based ASIC. Structured ASICs per-unit costs are up to 70% less than an equivalent FPGA. They offer far greater flexibility than an ASSP solution and typically at a lower per-unit cost. Simply put: structured ASICs are the most cost effective solution for mid-volume applications ranging from 5k to 250k units per year.

2. FPGA-to-ASIC Conversion Methodology

FPGA-to-ASIC conversion methodology allows designers to enjoy most of the benefits of both FPGA and ASIC technology. This is possible by first prototyping with an FPGA and then, once the design is proven, converting to a structured ASIC for full production. The following figure, illustrates this methodology flow.

This methodology provides the most cost effective solution for all but the smallest and largest volume applications. To achieve an even greater cost reduction, multiple FPGAs on the board can be converted into a single structured ASIC.

The following sections describe how the advanced features and performance capabilities available in structured ASIC technology can play an important role in common real-world applications.

3. Using Structure asic technology for SoC Applications

System-on-Chip (SoC) applications typically contain an embedded microprocessor with a standard system bus structure, supporting communication/control IP, high-speed memory interfaces and some custom logic designed specifically for that application. The following figure illustrates a common SoC application using an ARM processor.

Structured ASIC devices typically provide a ring of mask programmable I/O cells capable of supporting a wide range of I/O standards, such as the I/O illustrated in the sample SoC application. For example AMI Semiconductor’s XPressArray-II structured ASIC product supports everything from SSTL for high-speed DDR interfaces to I/O cells designed specifically to support PCI-X 2.0 interfaces. This rich set of high-speed configurable I/O enable the communication interfaces commonly found in SoC applications.

Structured ASIC fabrics can support soft synthesizable IP to implement embedded microprocessor and companion control and communication IP required by the application. This flexibility supports different SoC applications for different markets using the same base architecture. Even high-end applications requiring high-speed cache memory can be supported using standard structured ASIC base architectures due to the availability of the very high-speed embedded block RAMs.

Given its highly configurable nature combined with the availability of high-speed block RAMs, mask programmable I/O and a full line of soft synthesizable IP, structured ASIC technology is capable of supporting many of today’s demanding SoC applications.

4. Using Structured ASIC Technology for DSP Applications

When most people think of DSP applications, they automatically think digital signal processor and why not? That is what the acronym “DSP” stands for. But DSP applications don’t always include a processor. In fact, many designers prefer to unroll the DSP software algorithm into dedicated hardware solutions.

There are many reasons designers prefer hardware algorithms. One obvious reason is that pipelined hardware algorithms can execute DSP functions such as FFT and FIR filters significantly faster than software algorithms. Not only are hardware algorithms faster, they also consume fewer gates and fewer dollars. A 16-bit middle-of-the-road DSP processor can easily reach 50k gates and cost close to a half a million dollars. By comparison, a FIR filter implemented directly in hardware would be less than 10k gates and would cost just a few thousand dollars in either development cost or license fees. It is easy to see why hardware algorithms are the preferred solution for DSP applications that do not have a hard requirement for in-system programmability.

Structured ASICs fully support the hardware algorithms required for most DSP applications with technology capable of soft single-cycle 18×18 multipliers at speeds greater than 200 Mhz, which are faster than the hard embedded multipliers available in the advanced FPGAs. In addition to the multipliers, most structured ASIC suppliers offer pre-built and pre-verified IP such as Reed Solomon Encoders/Decoders, Viterbi Encoders/Decoders, Interleavers and Fast Fourier Transform/Inverse. For more fundamental functions, software tools are available to convert either “C” or Matlab algorithm descriptions directly into RTL.

5. Using Structured ASIC Technology for Comm Applications

Structured ASIC technology is well suited to a variety of bridge and router functions. The following figure illustrates a NPSI to SPI-4.2 bridge used to interface a network processor on a line card to a switch fabric across a backplane.

The availability of high-speed I/O cells capable of supporting gigabit data rates is critical to this type of application. In addition to the high-speed IO, a Dynamic Phase Alignment (DPA) PHY is usually required enabling the capture of DDR signal data, regardless of process, voltage and temperature variations. The DPA also adjust for skew between the data and clock signals due to board, trace and connector related factors. Due to tight timing constraints the DPA is normally supported as either a hard or firm macro. Hard macros are embedded in the base architecture of a structured ASIC while firm macros are implemented in the custom logic. Thus, firm macros have the advantage of only consuming resources if required for the application.

Other communication protocols that can easily be supported with structured ASIC technology include PCI-X 2.0 at both 266 Mhz and 533 Mhz, PCI-X 1.0 at 133 Mhz, USB 1.1 and 2.0 Controllers, 10/100/1000 Ethernet MACs, CAN Controllers and I 2C. With the ability to support a wide range of communication protocols structured ASICs are capable of supporting many of today’s communication applications.


Structured ASIC technology, such as AMI Semiconductor’s XPressArray-II, fills the gap between high piece-price FPGAs and high-NRE cell-based ASICs. Combined with AMI Semiconductor’s FPGA conversion expertise, XPressArray-II with its many FPGA-compatible features is an excellent vehicle for supporting the FPGA prototyping, ASIC production methodology across a wide range of applications.

About the Authors:

Rick Mosher, IP Product Manager, Structured Digital Products

Rick Mosher has more than eight years of engineering experience managing the design, verification and integration of complex digital logic blocks used to facilitate digital and mixed-signal ASIC products.
With a focus on FPGA, ASIC and PCB design coupled with product and system architect experience, Mosher possesses the skills necessary to aid AMI Semiconductor in developing digital IP roadmaps, analyzing market data and providing customer support for the structured digital product business unit.

As a system architect, Mosher designed the high-level system architecture of a multimode gigabit SerDes core and supported system-on-chip (SoC) designs for customer ASICs.

Before AMI Semiconductor, Mosher was a senior member of the design team responsible for the development of digital hardware used to enable TDMA and CDMA wireless systems for Nortel Networks. During his tenure at Nortel, Mosher was responsible for FPGA, ASIC and PCB design. Additionally, Mosher was the verification prime on the team, responsible for the system level verification of multi-million gate ASIC designs.

A published writer and expert speaker, Mosher’s education has been focused on telecom and computer engineering.

Bob Kirk, Director, Structured Digital Products System Architecture and Application Engineering

Bob Kirk is currently responsible for the planning and development of AMI Semiconductor’s (NASDAQ: AMIS) XPressArray™ structured ASIC product line. With extensive knowledge and experience in gate arrays, standard cells, structured ASICs, and FPGA/ASIC-to-ASIC conversions, Kirk has the expertise and capability to advance AMI Semiconductor’s market share and leadership position in the market.

A dedicated executive at AMI Semiconductor, Kirk started his professional career at AMIS in 1973 and has since held multiple management and engineering positions focused on CAD/EDA tools, standard cell library development and structured ASIC architectures.

During his tenure at AMIS, Kirk’s notable achievements have included establishing the Twain Harte research center focused on research and development of advanced VLSI CAD tools using artificial intelligence programming techniques and the development of AMI Semiconductor’s leading FPGA-to-ASIC conversion service.

A seasoned presenter and writer, Kirk has participated in numerous technical conferences, including DAC, CICC, WesCon, and DesignCon, and has been published in top trade magazines. He has also taught Internet seminars on FPGA conversions and recently took part in a technical debate on structured ASICs, sponsored by IEE. Kirk graduated Magna Cum Laude from the University of Santa Clara with a bachelor’s degree in electrical engineering and computer science.

Leave a Reply

featured blogs
Jul 20, 2024
If you are looking for great technology-related reads, here are some offerings that I cannot recommend highly enough....

featured video

Larsen & Toubro Builds Data Centers with Effective Cooling Using Cadence Reality DC Design

Sponsored by Cadence Design Systems

Larsen & Toubro built the world’s largest FIFA stadium in Qatar, the world’s tallest statue, and one of the world’s most sophisticated cricket stadiums. Their latest business venture? Designing data centers. Since IT equipment in data centers generates a lot of heat, it’s important to have an efficient and effective cooling system. Learn why, Larsen & Toubro use Cadence Reality DC Design Software for simulation and analysis of the cooling system.

Click here for more information about Cadence Multiphysics System Analysis

featured paper

Navigating design challenges: block/chip design-stage verification

Sponsored by Siemens Digital Industries Software

Explore the future of IC design with the Calibre Shift left initiative. In this paper, author David Abercrombie reveals how Siemens is changing the game for block/chip design-stage verification by moving Calibre verification and reliability analysis solutions further left in the design flow, including directly inside your P&R tool cockpit. Discover how you can reduce traditional long-loop verification iterations, saving time, improving accuracy, and dramatically boosting productivity.

Click here to read more

featured chalk talk

Automotive/Industrial PSoC™ High Voltage (HV) Overview
Sponsored by Mouser Electronics and Infineon
In this episode of Chalk Talk, Amelia Dalton and Marcelo Williams Silva from Infineon explore the multitude of benefits of Infineon’s PSoC 4 microcontroller family. They examine how the high precision analog blocks, high voltage subsystem, and integrated communication interfaces of these solutions can make a big difference when it comes to the footprint size, bill of materials and functional safety of your next automotive design.
Sep 12, 2023