High-end FPGAs with embedded processors, DSP and memory blocks are now replacing entire ASICs. New device families have accelerated programming times by dedicating several general-purpose I/O pins to create wider configuration buses that can then revert back to their primary I/O functionality. Rising device complexities imply high pin counts, which bring about new challenges and added costs when integrating these devices on the PCB. Design teams must now implement changes to ensure they do not negate the cost and time-to-market benefits of using programmable logic in the first place.
The Growing I/O Complexity Challenge
FPGAs with 1000+ pin counts pose a problem when they are incorporated into the board schematic. Manually placing and connecting this multitude of pins is inefficient at best, especially when a minor modification in the FPGA design means time-consuming iterations in the board design. Despite rising pin counts, the pin pitches on the package have remained relatively constant, but pin densities on the PCB have significantly increased. The ensuing routing congestion implies that most PCB designers have to be highly skilled in high-density interconnect (HDI) manufacturing processes. The bottom line: PCBs containing FPGA devices with high pin counts create the need for more board layers at an additional 10% to 20% per layer of manufacturing costs.
Selecting and configuring the optimal I/O standard must be completed within the context of the PCB’s electrical characteristics. High-speed serial I/Os in new device families make interfacing between the FPGA and system board an extremely tricky problem. For example, multi-gigabit transceiver (MGT) technology is aimed at narrowing data paths significantly while dramatically increasing throughput. However, these high-speed I/Os bring new challenges. Instead of worrying about system timing, over/undershoot, crosstalk and proper termination, designer attention gets focused on issues such as dielectric loss, skin effects and deterministic/random jitter, and their impact on inter-symbol interference.
Three primary factors contribute to signal degradation and attenuation in differential, multi-gigabit signals. They are dielectric loss (as a function of length and board material), vias, and connector loss. Vias, depending on geometry, can contribute between 0.5-1.0 dB of loss per via, against total loss budgets that typically range from 10-15 dB. Thus, most FPGA manufacturers recommend that MGTs be placed along the FPGA’s perimeter to eliminate the need to drop vias down to internal signal layers. Careful stack-up planning is essential for these signals, achieving carefully calibrated differential impedance, per FPGA manufacturer specifications.
To further frustrate the situation, FPGA I/O designs are fluid. No other silicon technology has offered this level of device interface flexibility. Many PCBs have been re-spun because the board and the FPGA design teams did not have the I/O design synchronized. This paper proposes a solution that bridges the widening gap between FPGA and PCB design flows at a time when high-pin count devices with new I/O functionality are driving significant increases in PCB manufacturing costs and overall time-to-market.
A Break from Tradition
The FPGA design flow uses a language-based approach, while the PCB uses a schematic-entry methodology. Using conventional flows with less complex devices, it was acceptable that FPGAs and PCBs were conceived in disparate design environments. However, this traditional independence of the FPGA and the PCB design teams has resulted in an “over the wall” serial approach where:
• The FPGA designer defines the top level block of the design, thus establishing the logical signals.
• The FPGA designer locks specific signals (clock signals, specific high-speed signals) during the FPGA synthesis step.
• The FPGA vendor’s place and route software automatically assigns the remaining FPGA top-level signals to physical device pins and creates the FPGA pin map file.
• The FPGA team transfers the pin mapping information to the PCB design team where the librarian creates a definition for the FPGA device.
• The PCB designer instantiates the FPGA symbol into the PCB schematic.
• The PCB schematic is driven into PCB place and route (P&R).
|Figure 1 : The traditional approach to FPGA I/O design is prolonged and prone to errors, since design teams must iterate through the entire FPGA-PCB design flow.|
Transferring the FPGA I/O design data into the PCB flow often involves manual data re-entry (between steps 3 and 4). Each pin is associated with a logical signal name, physical pin number, pin direction, pin-bank (pin swap group), FPGA device generic pin name and differential signal pin pair. Thus, a 1,000-pin device means that the PCB librarian will need to enter 6,000 pieces of data without any errors. Large pin-count symbols need to be fractured so that they may fit on a schematic sheet. The effort needed to create and manage these fractured symbols can range from days to weeks. Updating schematic connectivity each time the FPGA to signal pin mappings change is also a prolonged, error-prone process. If the logical signal name and physical pin number are not synchronized between the two flows, the FPGA may not operate once placed on the PCB.
In a typical FPGA P&R flow the I/O design is bound to change, since P&R leverages the “I/O assignment freedom” to meet FPGA timing constraints. A FPGA designer must take additional steps to lock the I/O design so that it will remain constant as the design evolves. Because the physical integration of the FPGA device onto the PCB design is quite expensive to maintain for high pin-count devices, design teams often lock the FPGA I/O design early in the process. Locking the I/O design alleviates FPGA-PCB integration maintenance costs, but also eliminates any chances of lowering the PCB manufacturing costs. Many design teams lock the I/O assignments early on and then find that they need to alter the FPGA I/O design to meet PCB routing or performance requirements. Unprepared to effectively deal with FPGA I/O change, these design teams often encounter design delays.
Constraints on Either Side
The constraints can be divided into two groups, the FPGA constraints and the PCB layout constraints. The FPGA is constrained by the timing requirements of the design (timing constraints), the capacity and architecture of the device (routing constraints) and the I/O standards applied to the I/O buffers (I/O constraints). The introduction of configurable I/O ASIC macro cells has meant greater flexibility within each device to support a wide range of signaling standards, but this imposes constraints in terms of which of these standards may be used in close proximity to each other. To maximize this flexibility, the devices group signals into I/O banks, further complicating the assignment rules. Each of these types of constraint influences the I/O assignment.
On the board side, optimum I/O assignment depends on the number of routing layers available and the orientation of the device on the PCB (routing constraints). In addition to the routing constraints, the PCB layout may have to meet Signal Integrity (SI) and timing constraints for the overall system design (SI and timing). Since these SI and timing constraints limit the length, clearance and other physical aspects of the board traces, they also influence the pin location of the I/O ports. The following lists the constraints that influence I/O design:
• FPGA timing
• FPGA routability
• FPGA I/O
• PCB routability
• PCB SI and timing
Since these constraints are managed by different designers (e.g. FPGA designer, PCB designer, and SI designer) and influence the same I/O assignment process, it is a difficult task to co-ordinate.
Bridging the FPGA-PCB Divide
The FPGA designer must satisfy synthesis and P&R constraints to meet timing specifications. Meanwhile, the PCB designer must constrain the design on the back-end to meet timing and SI requirements at the system level. As complexity rises, these constraints may conflict between the two design flows.
The first problem to solve is to raise the level of communication between the two design teams. Another key issue is to ensure consistency between the tool sets used in the HDL , FPGA and PCB environments. The language-based HDL representation of the FPGA must be properly represented as a schematic symbol containing the pin assignment data, as well as the appropriate links to the PCB layout tool. Eventually, these two design worlds must be synchronized through proper FPGA pin assignments on the PCB, and represented in the schematic symbol and PCB footprint database — yet by different design teams using completely different tool sets.
For example, a PCB may contain several high pin-count FPGAs that are being designed concurrently in order to meet aggressive time-to-market goals. Pin-out changes in each FPGA package must be continually reflected into the PCB schematic and layout design database. High-speed SI analysis tools for the PCB must have access to verification models for I/O drivers and receivers. Routing of the PCB for either completion, or to meet high-speed timing, may also require pin-out changes to the FPGA. In this dual-track process, the FPGA designer may use tools from both an EDA supplier as well as the FPGA vendor. The PCB designer could use tools from another EDA supplier who may or may not necessarily be the same as the FPGA tools supplier.
A major hurdle is to transfer the results of the FPGA P&R tools into the schematic and PCB layout tools. As stated earlier, this process could take over a week if done manually for a single 1,000+ pin FPGA. As the concurrent FPGA-PCB design process continues, the pin-outs change (typically 4-6 times) and without a totally automated FPGA tool to PCB schematic symbol and geometry transfer process, design schedules would be missed. With a PCB design system that understands the pin swapping and driver rules of the FPGA, these pin changes can be made in the PCB environment and then automatically reflected back to the FPGA tools.
To ensure proper performance, a high-speed verification must be performed which includes the exact routing on the PCB. With the multi-gigabit speeds now commonplace, FPGA vendor-supplied design kits must contain accurate IBIS , Spice or VHDL- AMS models. With these models, and PCB verification tools that can analyze in the GHz range, the entire design can be verified for SI and performance.
Often, the design teams may be based in different locations worldwide, as is often found in large organizations. This requires a built-in data management methodology that enables the designers to jointly work on the integration of an FPGA on the board and to keep track of every change made by any one of them. Therefore, the key to the problem of getting these two tool sets to work together is a tight interfacing between the tools in both flows.
As such, design teams could potentially eliminate iterations if they collaborate up front during the FPGA I/O design stage. There is an immediate need for concurrent, interactive design methodologies—unique to FPGA and PCB implementation—that provide the highest probability of creating a routable design, meeting SI and timing requirements on the first pass. New integrated system design tools, such as I/O Designer from Mentor Graphics, enable a collaborative environment specifically with these needs in mind.
|Figure 2: The I/O Designer flow manages and controls the way pins can be swapped during PCB layout while ensuring that these swaps do not violate FPGA technology rules.|
Consistency, Automation and Scalability
Most FPGA I/O design occurs at the logical level of abstraction in the design process. In reality, the I/O design must exist at the physical level to complete the PCB design process. The situation is further complicated by the priority given to each set of constraints during the design process.
If the goal is to have a prototype of the board as soon as possible, then the pin-out must be fixed early in the design process. Ideally, the PCB layout designer should determine the pin assignment during the PCB layout process so that the PCB constraints are met and the PCB optimized, while all FPGA constraints are automatically applied. In the past, the I/O assignment was done automatically by the FPGA vendor P&R tools with little regard for the PCB requirements. However, with the increasing complexity of the PCB this process needs to be managed by the design team. Therefore, the typical process today is to define these constraints up-front before going into the synthesis and P&R process. Often these constraints are defined in a tool-specific constraint file that passes directly into the synthesis tool and is then forwarded to the P&R tool. Defining the constraints through the ASCII constraint file requires the designer to understand the FPGA I/O pin details and assignment rules (FPGA I/O constraints) before being able to assign an I/O port. Since it is typically the FPGA designers who do this job, they probably are not aware of the PCB layout details and so will not optimize this part of the design.
The I/O design process is the first step in optimizing the pin assignment on the connectivity of the selected FPGA to all surrounding components on the board. I/O Designer addresses this issue up front. To finalize the board optimization process the tool manages and controls the way pins can be swapped during PCB layout, while making sure that these swaps do not violate any of the FPGA technology rules. I/O Designer enables users to step through the design flow in a unique manner, right from the top-level HDL description to the PCB-level symbol, as well as to the physical pin information needed by the FPGA P&R tools. It back-annotates any FPGA modifications made in P&R, as well as in PCB schematic and layout tools. The tool thus provides offers a central environment for the digital engineer designing the HDL and the physical implementation of the FPGA, as well as for the board designer using the device symbol. Three key features and benefits are outlined below.
Consistency: Whenever one designer changes the pin-out, the changes should be automatically propagated to the rest of the design tools involved in FPGA integration. If the PCB designer decides to swap two pins, it influences the internal routing of the FPGA. I/O Designer ensures that the FPGA and PCB flows are consistent. As a data management tool, it monitors each flow and manages all changes that occur. The tool tracks PCB pin swaps and updates the relevant files on-the-fly. I/O Designer thus generates FPGA P&R constraints based on the HDL design and pin I/O assignment process, and creates the necessary symbols, schematics and hierarchical associations based on the “post-route” pin data.
Automation: It is relatively easy to automate the FPGA P&R process and manage the timing and I/O constraints. The PCB layout process, however, is difficult to totally automate since there are many variables to consider. During PCB layout, the designer typically routes the board while trying to avoid violating any of the timing, SI and routability constraints. Therefore, any tool designed to integrate an FPGA on a board should focus on automating the FPGA constraints management, while allowing the designer to concentrate on “difficult to automate” tasks during PCB layout. The tool should have a built-in library containing all the necessary device information from vendors such as Altera, Actel and Xilinx to allow the constraints to be applied, as well as to enable a good integration to all the tools in the FPGA and PCB design flows. I/O Designer uses the I/O design information to automatically generate the necessary symbols and schematics and maintains these schematics if the I/O assignment changes. If the changes come from the FPGA side, then the schematic is simply updated and the changes propagated to the PCB layout tools.
Scalability: Scaling up or down to a larger or smaller device during the design phase is a very common step. Since each of the pins on an FPGA device may have special properties (as we have discussed earlier and defined as FPGA I/O constraints), a designer needs to take the migration to a larger or smaller device into account when assigning the I/O pins. Using I/O Designer, the team does not have to re-assign the I/O if they decide to switch to a larger or smaller FPGA. Since changing the I/O design always causes an additional re-spin of the board design, it is crucial to avoid this step if it is not really necessary.
Leveraging FPGA’s Flexible I/O
A modern FPGA architecture contains programmable I/Os that may support more than 50 different I/O standards. A range of single-ended and low voltage differential signal (LVDS) I/O standards are typically available. And while FPGA I/O designs are fluid, they are only flexible up to a point. Modern FPGA device architectures group collections of pins together into “pin-banks.” Pins within a pin-bank share some common characteristics, like a reference voltage, and are generally swappable. However, pins in different pin-banks may have incompatible I/O standards assigned to them, which results in varying situations.
One situation is when a PCB designer asks for a FPGA I/O pin change to meet PCB interconnect performance specifications or for PCB routability. Another situation could be when an initial pin change creates an I/O standard co-habitation violation, forcing an existing signal to be moved into a new pin-bank. A final situation appears when relocated signals from the previous situation create an I/O standard co-habitation violation, forcing existing signals to be moved to a new pin-bank.
Figure 3: Using the same pin-bank may result in crossing signals.
LVDS signal pairs are used primarily for high-speed signals where SI issues are a concern. When an LVDS I/O standard is assigned to a signal in the FPGA device, the FPGA signal will use two pins on the FPGA package. LVDS signals may have performance benefits on the PCB, but they also impose additional constraints. LVDS trace pairs must: (1) be matched in length to +/-10 percent and (2) maintain a fixed separation between the differential pair traces across their entire length.
Using too many LVDS I/O standards for FPGA logical signals could create the need to move up to a larger FPGA package with more pins. Not having access to LVDS I/O standards would imply performance limitations that many product design teams would find unacceptable. The ability to easily change from single- to dual-pin I/O standards (and back again) gives the entire design team the ability to explore meeting system performance constraints with the least number of LVDS I/O signals. In the end, minimizing LVDS usage reduces PCB manufacturing complexity and costs.
Building the I/O pin-banking rules into tools like I/O Designer (which the PCB designer could easily learn to use via an intuitive, easy-to-use GUI) unlocks the power and insight of the PCB designer to effectively participate in the FPGA I/O design process. Mastering concurrent FPGA and PCB team design of the FPGA I/O and automating the physical integration of the FPGA and PCB design flows allows design teams to use the flexibility of the FPGA I/O to reduce PCB routing congestion. A careful examination of modern FPGA architectures and their usage reveals interesting facts:
• Pins within a pin-bank are easily swappable.
• Signals within a bus in the design are generally assigned to the same pin-bank (to take advantage of easy pin swapping).
• Pin-banks may not represent the best physical design for a bus of signals in the design (Figure 3 shows why using the same pin-bank may force signals in the bus to cross over one another on the PCB).
By learning to effectively use multiple pin-banks to physically optimize the FPGA I/O and eliminate crossing signals within buses, it is possible to also reduce the number of signal layers required to manufacture the PCB, and thus lower costs.
Figure 4: Using a tool with built-in I/O pin-banking rules allows the PCB designer to participate in the FPGA I/O design process. For example, designers can avoid crossing signals by effectively using m ultiple pin-bank s.
With today’s high-speed, high gate count, high pin count FPGAs the only constant in FPGA design is the changes that occur along the way, both at the interconnect level—to meet timing and loss requirements—and at the pin assignment stage within the FPGA itself. The great benefit of design flexibility offered by the FPGA is also one of the biggest nightmares for board designers. Companies would be wise to examine existing processes closely, making sure that the significant flexibility and power offered by today’s FPGAs doesn’t backfire, becoming a doorway for potentially significant PCB implementation problems. New tools such as I/O Designer from Mentor Graphics not only automate the schematic connectivity required for PCB layout and verification, but they also document which signal connections are made to which device pins and indicate how these pins map to the original board-level bus structures. With the right software tools and close collaboration between the parallel paths of FPGA and PCB design, weeks can be trimmed from FPGA design and implementation schedules, providing significant overall cost savings in the long term.