feature article
Subscribe Now

Powering FPGA-based Boards

Increased gate counts and higher clock speeds in programmable logic ICs have resulted in higher current requirements while smaller device geometries are driving lower core supply voltages. Simultaneously, new communications and memory technologies (DDR, DDR2) are requiring additional new supply voltages. Table 1 shows this low voltage trend in the generational progression of Xilinx FPGAs (Field Programmable Gate Arrays).

Table 1. Voltage Requirements of Xilinx FPGA Families

Family

Geometry Vcc core

Spartan/XL

0.35 µm

3.3V

Virtex

0.22 µm

2.5V

Virtex-E

0.18 µm

1.8V

Virtex-II

0.15 µm

1.5V

Virtex-II Pro

0.13 µm

1.5V

Spartan -3

0.09 µm

1.2V

These trends are forcing board designers to utilize more and higher performance power supplies. Fortunately, the latest generation of low voltage power management ICs are keeping pace with the challenges presented by these high-performance boards. (1)

Power Requirements of the Latest Generation of FPGAs

A large part of the value of FPGAs is their flexibility. For example, Altera offers 14 different products in their Stratix/Stratix GX family of FPGAs. These products range in functionality from 10,570 logic elements (LEs) to over 79,000 LEs. (2) In terms of power consumption, the smallest version clocking at less than 100MHz will require less than 1Amp of peak current for the core logic (at 1.5V), whereas the largest version will require almost 14Amps for the core logic when clocked at 300MHz (3). Xilinx’s latest generations of FPGAs are offered in an even wider range of capabilities and power requirements.

But these are maximum power numbers assuming very high logic gate utilization. One of the issues faced by FPGA-based board designers is the uncertainty about the actual power requirements of the system, since the gate-level design is usually not finalized before the hardware is first generated (the flexibility of FPGAs allows this, so engineers take advantage of it!) Another major issue that the power supply designer needs to deal with is dynamic load requirements. The FPGA load may quickly go from an inactive, low current state to a fully processing state, and accurate regulation needs to be maintained.

It is beyond the scope of this article to go through the details of the equations and design trade-offs between regulation, dynamic load response, power efficiency, board space, and cost. Suffice it to say that the logic and I/Os in FPGAs can be much more flexible than the power supply circuits that are powering them. This often means that a high performance, worst case supply should be built into the system from the beginning.

Core Logic Power: In large FPGAs, the logic core generally has the most demanding current requirements, up to tens of Amps depending on the number of gates being used and the clock frequency. This core logic is designated VCCINT by both Xilinx and Altera. On the positive side, once the FPGA family is selected, the core logic supply voltage is set (as shown in Table 1, for example). Tools are available to determine the current consumption of the core logic on the FPGA company’s website, or maximum current estimates can be found in FPGA power applications guides (such as the ones found at www.intersil.com/data/AG.)

I/O Power: In the latest generation of FPGAs, over 15 different I/O standards are offered with voltage levels equal to 1.5V, 1.8V, 2.5V or 3.3V, depending on the I/O standard. Since I/O standards can be set independently by block in the FPGA, more than one I/O voltage for a single FPGA is possible. I/O current requirements are dependent on the number of I/Os used and the clocking speed. Generally, even in the largest FPGAs, I/O currents are less than 3Amps. Because the I/O voltages required by an FPGA are determined by which devices the FPGA is interfacing with, often the low voltage supply generated for the FPGA’s I/O can be shared to power the I/O of the companion device and possibly other circuits.

VAUX Power : The “auxiliary” supply is important for the latest generation of Xilinx FPGAs because it is tied into the JTAG, DCM, and other circuitry. It is designated VCCAUX , and is usually 3.3V or 2.5V. VCCAUX must be sufficiently decoupled in order to avoid power supply transients coupling into the FPGA’s clock

Implications on Power Supply Designs

Powering FPGA-based boards requires the generation of at least one, often 2 or 3 voltages below 3.3V. Typically the FPGA’s core logic supply is the lowest voltage required on the board, and often the largest current. Since the power dissipated in linear regulators is proportional to both the voltage drop and the current required, it is often best to use a switching DC-DC regulator for the core logic supply, because they offer much higher efficiency. Whether or not the I/O supplies should be supplied by a switching DC-DC regulator or a linear regulator is dependent on the amount of current required.

Single IC Solutions for Powering FPGAs

Figure 1 below shows a single IC solution for generating 4 supply voltages from a single +5V VIN. A more detailed schematic is available at www.intersil.com/Xilinx or www.intersil.com/Altera. The ISL6521 implements a highly efficient synchronous buck design and in addition includes three linear regulator/controllers, which can provide additional voltages to the board. I /O and IAUX currents less than 120mA can be supplied directly from the linear regulator drive pins (as shown here for 2.5V and 1.8V) or they can be used to control an external transistor (as shown here for 3.3V).

Current IC and module technology can attain very high levels of isolation between each output on a single IC or in a single package. The cause of board-level, supply coupling is more likely to be poor external component selection and layout mistakes than having 2 supplies share one IC.

Figure 1. Four Output, Low Voltage Power Supply

The ISL6521 automatically initializes upon receipt of input power. The Power-On Reset (POR) function continually monitors the input bias supply voltage at the VCC pin. The POR function initiates soft-start operation after the bias supply voltage exceeds its POR threshold. All voltages rise monotonically and in less than 40ms, which is often a requirement for FPGAs.

If only a single I/O voltage and the core logic voltage are required, then these can be produced at very low cost and in package sizes as small as an 8-pin SOIC. Figure 2 below shows such a solution. Again VCCINT is supplied by the switching DC-DC regulator, and the I/O voltage is supplied by the linear regulator/controller, using an external pass element to minimize the heat dissipated in the ISL6528.

Figure 2: Two Output, Low Cost Power Supply

This configuration is applicable for VCCINT from 0.8V to 3.3V and up to approximately 15A, and V I/O from 0.8V to 3.3V and up to 4A. Simulation tools are available at http://www.intersil.com/isim/.

Just Make It EASY!

The technology for high performance switching DC-DC power converters has progressed dramatically in the past few years, and it is now possible to purchase devices that require only a few external components (usually an inductor, a few capacitors and a few resistors) to generate a well-regulated supply voltage. These ICs also often include features such as over-voltage protection, supply sequencing capabilities and soft-start.

Figure 3: Small, Easy-to-Implement, High Performance Power Supply

A good example is the EL7566 6Amp switching DC-DC converter from Intersil, which is part of a family of products that can supply between 1 Amp and 6Amps of output current. The EL75Xx family can convert down from VIN =3.0V to 6V to as low as 0.8V (for VOUT.) This covers all the major FPGA core and I/O voltage levels. The design shown in Figure 3 can be implemented in less than 0.72 sq. Inches (4). The I/O blocks of the FPGA will need to be powered by a separate linear regulator or a separate DC-DC regulator.

 Conclusion

A variety of multi-output and low component count power supply IC solutions are available to board designers that are confronted with the increasing number of low voltage supplies required by the latest generation of FPGAs.

Notes:

  1. Refer to Applications Guide for Powering Xilinx FPGAs and DDR Memory or Applications Guide for Powering Altera FPGAs and DDR Memory at www.intersil.com/data/AG
  2. Source: www.altera.com/products/devices
  3. Source: Altera Stratix Power Calculator.
  4. Source: EL7566 Evaluation Board documentation at http://www.intersil.com/data/tb/tb415.pdf


9 thoughts on “Powering FPGA-based Boards”

  1. Pingback: www.cpns2016.com
  2. Pingback: Bdsm
  3. Pingback: orospu
  4. Pingback: DMPK Studies
  5. Pingback: read this
  6. Pingback: Engineer X

Leave a Reply

featured blogs
Jul 29, 2021
Circuit checks enable you to analyze typical design problems, such as high impedance nodes, leakage paths between power supplies, timing errors, power issues, connectivity problems, or extreme rise... [[ Click on the title to access the full blog on the Cadence Community sit...
Jul 29, 2021
Learn why SoC emulation is the next frontier for power system optimization, helping chip designers shift power verification left in the SoC design flow. The post Why Wait Days for Results? The Next Frontier for Power Verification appeared first on From Silicon To Software....
Jul 28, 2021
Here's a sticky problem. What if the entire Earth was instantaneously replaced with an equal volume of closely packed, but uncompressed blueberries?...
Jul 9, 2021
Do you have questions about using the Linux OS with FPGAs? Intel is holding another 'Ask an Expert' session and the topic is 'Using Linux with Intel® SoC FPGAs.' Come and ask our experts about the various Linux OS options available to use with the integrated Arm Cortex proc...

featured video

Breakthrough FPGA news from Intel

Sponsored by Intel

As part of the numerous portfolio announcements associated with the launch of the 3rd Gen Intel® Xeon® Scalable processor, Intel also disclosed some breakthrough FPGA news: Intel® Agilex™ FPGAs now deliver industry-leading power efficiency and performance.

Click here for more information about Intel® Agilex™ FPGAs.

featured paper

Intel® Agilex™ FPGAs target IPUs, SmartNICs, and 5G Networks White Paper

Sponsored by Intel

Security challenges in the form of cyberattacks and data breaches loom ever larger as attacks on high-speed networks multiply. Massive amounts of data are at risk but so are physical resources, including critical physical infrastructure. Cryptography and authentication represent potent countermeasures. The latest members of the Intel® Agilex™ FPGA and SoC FPGA families feature hardened crypto blocks paired with MACsec soft IP to help mitigate the risks and limit the effects of these cyberattacks.

Click to read more

featured chalk talk

How Trinamic's Stepper Motor Technologies Improve Your Application

Sponsored by Mouser Electronics and Maxim Integrated

Stepper motor control has come a long way in the past few years. New techniques can give greater control, smoother operation, greater torque, and better efficiency. In this episode of Chalk Talk, Amelia Dalton chats with Lars Jaskulski about Trinamic stepper solutions and how to take advantage of micro stepping, load measurement, and more.

Click here for more information about Trinamic TMCM-6110 6-Axis Stepper Motor Driver Board