Design For Manufacturing (DFM) was a headline darling for a while and somehow disappeared off the radar, even as debates continued as to whether all the DFM fuss was about nothing. In fact, much of what constitutes DFM, originally implemented as point tools by young upstart companies, has quietly been subsumed into mainstream flows by mainstream tool providers, thanks in part to the traditional EDA start-up/buy-up cycle.
Fundamentally, design and verification have gone from modeling the idealized results of a manufacturing process to modeling the actual manufacturing steps in much greater detail. The criticality and accuracy required have evolved so that what was once a conceptual shift, moving manufacturing considerations into the design sphere, have now become standard, and the tools are now on that general trend of increasing precision and performance.
Recently, both Mentor and Synopsys made some announcements enhancing their respective DFM capabilities. While there was overlap in the issues addressed, the main points addressed by the releases were different. Mentor has placed specific focus on the Chemical-Metal Polish (CMP) phase of manufacturing, while Synopsys has taken the integration of DFM closure closer into the design loop.
Standing on its side
A funny thing happened somewhere along the way as horizontal dimensions shrank. Once upon a time, metal lines were thin, flat wires of some width and length, and all the verification scrutiny was on the horizontal dimensions to make sure that the lines could be manufactured reliably. In the thinking of the day, it would have seemed silly to take such lines and stand them on their sides, with the wide part of the line actually going vertically into the silicon. Yet, over time, that’s exactly what’s happened. The horizontal width has shrunk down to where it can be about half the thickness of the metal. That means the line is taller than it is wide; it’s like an old line on its side.
But the design focus has fundamentally remained concentrated on the horizontal dimensions, and that’s no longer good enough. Metal lines aren’t uniformly distributed over the top of a chip; there are parts with lots of metal interconnect and parts that are relatively barren. The problem is that, with the thickness of the metal being significant, the surface of the die will now ripple, based on where there is or isn’t any metal. And the depth of that ripple actually matters, since the focal length of the next lithography step will be critical. The machines can’t focus both on the top of the metallized portions and on the top of the metal-less portions with equal precision. Making matters more complicated still, the expected variation in the thickness of the metal is moving to 20% at the 32-nm node.
So the solution has been to add “metal fill” – that is, put in metal that’s not connected to anything just to fill the space and keep the surface of the chip more or less level. Of course, adding too much of this isn’t great either, since these floating blobs can couple to active metal. So you want enough fill but not too much.
Mentor sees an active transition occurring here from a rules-based approach to a more comprehensive model-based approach, and they’re incorporating this into their Calibre tool. On one hand, you can think of models as just much more sophisticated rules, but there’s a more subtle difference. Rules are derived by analyzing the effects of various layouts and inferring rules. It is assumed that if you follow the rules, you will be okay. But there’s a layer of indirection, and, even after following the rules, you need to do some verification to ensure that things worked out ok. The model-based approach uses analysis directly when creating the metal fill in order to place the fill in a manner that is more or less correct by construction (or as nearly correct as the model can provide), eliminating the “fill-analyze-tweak” loop and replacing it with an “analyze-fill” step.
Mentor sees this transition occurring in phases, and they have structured their products accordingly. The first step is what they call their SmartFill product. Its role is to do a better job of traditional metal fill, striking a better balance between enough and too much fill. The next step involves pushing fill verification to the designer with their CMPAnalyzer tool. This allows designers to check more accurately the 3D impact of their metal layout and the possible variations in metal thickness. The final step involves a transition to model-based fill, which integrates the analysis and fill creation components together.
Steady as she goes
Synopsys, in the meantime, has turned its energy towards the fact that having a separate DFM convergence step is at best time consuming and at worst may not work, since it’s decoupled from the timing convergence step. The way things are done now, you do your place and route, check the DFM, and then change the design, rinse, and repeat, pulling out your hair here and there. With luck, you move towards a clean design. Without luck, you keep repeating until you have no more hairs left to pull out.
Their main emphasis, as embodied in their new IC Validator tool, is on providing incremental DFM checking during the design process so that convergence happens as the design progresses. DFM is optimized by the tools concurrently with timing so that they should be able to converge together.
IC Validator appears to be rules-based, but Synopsys has provided a new proprietary language, PXL, to allow creation of more sophisticated rules (although TCL can also be used if desired). Like the predecessor Hercules tool, IC Validator is what they call a “hybrid” tool in that both polygon-based and more modern edge-based rules can be accommodated.
Interestingly enough, they also highlight metal fill as one of the key DFM utilites. Coincidence? But rather than their message focusing specifically on the CMP element, they note that, whereas metal fill added during the place-and-route phase will always use “tracks” for the fill elements, IC Validator can allow for “trackless” metal fill, giving better coverage since the fill isn’t constrained to the tracking grid. And, just as a more or less uniform metal density is desirable on a given layer, the same is true for vias. So via fill operates on basically the same principle as metal fill.
The tool works in conjunction with the IC Compiler place and route tool so that when problems are detected, a constraint is fed back to the router so that the layout can be automatically tweaked to resolve the violation. Done in an incremental manner and in conjunction with timing constraints, the design remains in convergence each step of the way as the design progresses.
Links:
