If you design SoCs, then you use IP. Lots of it, probably. From different companies, some perhaps even from your own company.

And the good news is, it’s all perfectly documented – pins, registers, timing, everything. Right? So you know that just fitting it all together will give you a correct-by-construction design. Right?

Yeah… and then you wake up.

In fact, the RTL implementation may deviate from the spec, or there may be holes in the spec, or the black-box RTL may have invisible surprises. It’s enough to make you run back to the comfort of your pillow.

Jasper and Duolog, at the urging of ARM, have come together to try to solve some of this. The first key ingredient is a machine-friendly way of describing an IP block. And that would be IP-XACT. IP-XACT doesn’t describe the IP implementation; it’s simply (if “simple” can be used here) a specification of the metadata and the interface. Like a software function or object prototype. (To be clear, Jasper and Duolog didn’t create IP-XACT; it’s been around for a while, and they simply make use of it.)

Given spec’ed and implemented versions of an IP block, Duolog and Jasper can then confirm whether specs match RTL or black-box matches white-box. That’s the first of two tools that will be available.

The second will help assemble the IP blocks into a design and then verify that everything is connected properly. “How hard can that be?” you ask. Well, given that some connections may come and go over time or given various conditions (for instance, via multiplexing), and the fact that some IP can have hundreds (or more) of connections, it can actually get pretty complicated. The tools purport to handle these scenarios, including such timing details as latency.

This all got rolled out at DAC, so it’s available today. You can find out more in their release.