editor's blog
Subscribe Now

Imperas Gen 2

Imperas has launched their second-generation virtual platform technology. In so doing, they’re adding more capability as well as restructuring their product offering.

We’ve been following their OVPworld approach for a few years, now, Dick Selwood having covered the technology back in 2009. What was then OVPsim has morphed into three “DEV” products – C*DEV, S*DEV, and M*DEV for microControllers, microprocessors (S=Standard), and multicore, respectively. (The * is pronounced “star.”) Each of these has the capability of generating a system model comprising any of the many model components in their library, and it comes with the simulator for executing that model.

They’ve now announced their M*SDK product, which layers new debugging and analytic capabilities on top of the DEV products. These are the typical kinds of probing and profiling tools that a software developer will want to use in optimizing code and/or platform execution. They include:

  • Code coverage
  • Memory and cache analysis
  • Execution profiling
  • Instruction and function tracing
  • Fault injection
  • Protocol verification
  • Exception and interrupt analysis
  • OS task tracing
  • OS scheduler analysis
  • Memory protection verification
  • Shared resource introspection

They’ve also extended their code morphing approach to include references to models of processors that come with their own ISS. In other words, it’s not just a model – it’s a model plus a tool. Such a tool is a slave to the overarching simulator, but can be called to deliver quick, accurate responses to simulation events. Called ToolMorphing, it not only creates the model code on the fly, but binds (for lack of a better word coming to mind right now) an associated tool for that model if there is one.

Meanwhile, the venerable OVPsim has been relegated to use as their academic product. It’s still around, but is no longer featured as a commercial focus.

You can find more information in their release.

Leave a Reply

featured blogs
Jan 24, 2020
Someone has created a song by taking Pi, assigning each number to a note, and adding harmonies. The result is strangely captivating....
Jan 24, 2020
[From the last episode: We looked at the different ways memory can be organized in different kinds of systems.] Let'€™s look at a scenario: you run a restaurant, but you'€™re short on funds to hire people. So you'€™re your own chief cook and bottle-washer. You do everyt...
Jan 23, 2020
Embedded design trends typically revolve around three main ideas: faster data rates, smaller form factors and cost-effective solutions. Those design trends drive the theme for the 2020 Embedded Tech Trends forum: The Business and Technology Forum for Critical and Intelligent ...
Jan 22, 2020
Master the design and verification of next gen transport: Part One – Overview Master the design and verification of next gen transport: Part Two – High-Level Synthesis Master the design and verification of next gen transport: Part Three – Functional Safety M...

Featured Video

Automotive Trends Driving New SoC Architectures -- Synopsys

Sponsored by Synopsys

Today’s automotive trends are driving new design requirements for automotive SoCs targeting ADAS, gateways, connected cars and infotainment. Find out why it is essential to use pre-designed, pre-verified, reusable automotive-optimized IP to meet such new requirements and accelerate design time.

Drive Your Next Design to Completion Today with DesignWare IP® for Automotive SoCs