editor's blog
Subscribe Now

Imperas Gen 2

Imperas has launched their second-generation virtual platform technology. In so doing, they’re adding more capability as well as restructuring their product offering.

We’ve been following their OVPworld approach for a few years, now, Dick Selwood having covered the technology back in 2009. What was then OVPsim has morphed into three “DEV” products – C*DEV, S*DEV, and M*DEV for microControllers, microprocessors (S=Standard), and multicore, respectively. (The * is pronounced “star.”) Each of these has the capability of generating a system model comprising any of the many model components in their library, and it comes with the simulator for executing that model.

They’ve now announced their M*SDK product, which layers new debugging and analytic capabilities on top of the DEV products. These are the typical kinds of probing and profiling tools that a software developer will want to use in optimizing code and/or platform execution. They include:

  • Code coverage
  • Memory and cache analysis
  • Execution profiling
  • Instruction and function tracing
  • Fault injection
  • Protocol verification
  • Exception and interrupt analysis
  • OS task tracing
  • OS scheduler analysis
  • Memory protection verification
  • Shared resource introspection

They’ve also extended their code morphing approach to include references to models of processors that come with their own ISS. In other words, it’s not just a model – it’s a model plus a tool. Such a tool is a slave to the overarching simulator, but can be called to deliver quick, accurate responses to simulation events. Called ToolMorphing, it not only creates the model code on the fly, but binds (for lack of a better word coming to mind right now) an associated tool for that model if there is one.

Meanwhile, the venerable OVPsim has been relegated to use as their academic product. It’s still around, but is no longer featured as a commercial focus.

You can find more information in their release.

Leave a Reply

featured blogs
Mar 31, 2023
Learn how (and why) the semiconductor industry is moving towards chiplet-enabled multi-die systems in our research piece in MIT's Technology Review Insights. The post An Industry-Wide Look at the Move Toward Multi-Die Systems appeared first on New Horizons for Chip Design....
Mar 31, 2023
The Verisium Debug platform is optimized for scalability, supporting debugging of simulation runs and emulation, where support for loading large source files and handling huge amounts of probe data is a must. Join this free Cadence Training Webinar to learn how to automate yo...
Mar 30, 2023
Are you in desperate need of a program manager to instigate a new project or rescue an existing project that is spiraling out of control?...

featured video

First CXL 2.0 IP Interoperability Demo with Compliance Tests

Sponsored by Synopsys

In this video, Sr. R&D Engineer Rehan Iqbal, will guide you through Synopsys CXL IP passing compliance tests and demonstrating our seamless interoperability with Teladyne LeCroy Z516 Exerciser. This first-of-its-kind interoperability demo is a testament to Synopsys' commitment to delivering reliable IP solutions.

Learn more about Synopsys CXL here

featured chalk talk

Advantech Edge Gateways for Equipment Monitoring
Sponsored by Mouser Electronics and Advantech
One of the biggest challenges with equipment monitoring today includes one critical question: How do I integrate multiple data formats from different devices, equipment, meters, and sensors into my system? In this episode of Chalk Talk, Amelia Dalton chats with Eric Wang from Advantech about how the Advantech WISE-EdgeLink solution can help you navigate the challenges of data collection in edge applications. They also take a closer look at the benefits of the Advantech WISE-EdgeLink smart gateway family and show you how to get started using one of these smart gateways in your next edge application. 
Mar 1, 2023
4,070 views