editor's blog
Subscribe Now

Imperas Gen 2

Imperas has launched their second-generation virtual platform technology. In so doing, they’re adding more capability as well as restructuring their product offering.

We’ve been following their OVPworld approach for a few years, now, Dick Selwood having covered the technology back in 2009. What was then OVPsim has morphed into three “DEV” products – C*DEV, S*DEV, and M*DEV for microControllers, microprocessors (S=Standard), and multicore, respectively. (The * is pronounced “star.”) Each of these has the capability of generating a system model comprising any of the many model components in their library, and it comes with the simulator for executing that model.

They’ve now announced their M*SDK product, which layers new debugging and analytic capabilities on top of the DEV products. These are the typical kinds of probing and profiling tools that a software developer will want to use in optimizing code and/or platform execution. They include:

  • Code coverage
  • Memory and cache analysis
  • Execution profiling
  • Instruction and function tracing
  • Fault injection
  • Protocol verification
  • Exception and interrupt analysis
  • OS task tracing
  • OS scheduler analysis
  • Memory protection verification
  • Shared resource introspection

They’ve also extended their code morphing approach to include references to models of processors that come with their own ISS. In other words, it’s not just a model – it’s a model plus a tool. Such a tool is a slave to the overarching simulator, but can be called to deliver quick, accurate responses to simulation events. Called ToolMorphing, it not only creates the model code on the fly, but binds (for lack of a better word coming to mind right now) an associated tool for that model if there is one.

Meanwhile, the venerable OVPsim has been relegated to use as their academic product. It’s still around, but is no longer featured as a commercial focus.

You can find more information in their release.

Leave a Reply

featured blogs
Nov 23, 2022
The current challenge in custom/mixed-signal design is to have a fast and silicon-accurate methodology. In this blog series, we are exploring the Custom IC Design Flow and Methodology stages. This methodology directly addresses the primary challenge of predictability in creat...
Nov 22, 2022
Learn how analog and mixed-signal (AMS) verification technology, which we developed as part of DARPA's POSH and ERI programs, emulates analog designs. The post What's Driving the World's First Analog and Mixed-Signal Emulation Technology? appeared first on From Silicon To So...
Nov 21, 2022
By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize… ...
Nov 18, 2022
This bodacious beauty is better equipped than my car, with 360-degree collision avoidance sensors, party lights, and a backup camera, to name but a few....

featured video

Maximizing Power Savings During Chip Implementation with Dynamic Refresh of Vectors

Sponsored by Synopsys

Drive power optimization with actual workloads and continually refresh vectors at each step of chip implementation for maximum power savings.

Learn more about Energy-Efficient SoC Solutions

featured paper

Algorithm Verification with FPGAs and ASICs

Sponsored by MathWorks

Developing new FPGA and ASIC designs involves implementing new algorithms, which presents challenges for verification for algorithm developers, hardware designers, and verification engineers. This eBook explores different aspects of hardware design verification and how you can use MATLAB and Simulink to reduce development effort and improve the quality of end products.

Click here to read more

featured chalk talk

Chipageddon: What's Happening, Why It's Happening and When Will It End

Sponsored by Mouser Electronics and Digi

Semiconductors are an integral part of our design lives, but supply chain issues continue to upset our design processes. In this episode of Chalk Talk, Ronald Singh from Digi and Amelia Dalton investigate the variety of reasons behind today’s semiconductor supply chain woes. They also take a closer look at how a system-on-module approach could help alleviate some of these issues and how you can navigate these challenges for your next design.

Click here for more information about DIGI ConnectCore 8M Mini