editor's blog
Subscribe Now

Imperas Gen 2

Imperas has launched their second-generation virtual platform technology. In so doing, they’re adding more capability as well as restructuring their product offering.

We’ve been following their OVPworld approach for a few years, now, Dick Selwood having covered the technology back in 2009. What was then OVPsim has morphed into three “DEV” products – C*DEV, S*DEV, and M*DEV for microControllers, microprocessors (S=Standard), and multicore, respectively. (The * is pronounced “star.”) Each of these has the capability of generating a system model comprising any of the many model components in their library, and it comes with the simulator for executing that model.

They’ve now announced their M*SDK product, which layers new debugging and analytic capabilities on top of the DEV products. These are the typical kinds of probing and profiling tools that a software developer will want to use in optimizing code and/or platform execution. They include:

  • Code coverage
  • Memory and cache analysis
  • Execution profiling
  • Instruction and function tracing
  • Fault injection
  • Protocol verification
  • Exception and interrupt analysis
  • OS task tracing
  • OS scheduler analysis
  • Memory protection verification
  • Shared resource introspection

They’ve also extended their code morphing approach to include references to models of processors that come with their own ISS. In other words, it’s not just a model – it’s a model plus a tool. Such a tool is a slave to the overarching simulator, but can be called to deliver quick, accurate responses to simulation events. Called ToolMorphing, it not only creates the model code on the fly, but binds (for lack of a better word coming to mind right now) an associated tool for that model if there is one.

Meanwhile, the venerable OVPsim has been relegated to use as their academic product. It’s still around, but is no longer featured as a commercial focus.

You can find more information in their release.

Leave a Reply

featured blogs
May 16, 2021
https://youtu.be/_wup2MSTVks Made on Communication Hill, San Jose (camera Carey Guo) Monday: Intel eASIC: Linley and DARPA Tuesday: Please Excuse the Mesh: CFD and Pointwise Wednesday: Linley:... [[ Click on the title to access the full blog on the Cadence Community site. ]]...
May 13, 2021
Samtec will attend the PCI-SIG Virtual Developers Conference on Tuesday, May 25th through Wednesday, May 26th, 2021. This is a free event for the 800+ member companies that develop and bring to market new products utilizing PCI Express technology. Attendee Registration is sti...
May 13, 2021
Our new IC design tool, PrimeSim Continuum, enables the next generation of hyper-convergent IC designs. Learn more from eeNews, Electronic Design & EE Times. The post Synopsys Makes Headlines with PrimeSim Continuum, an Innovative Circuit Simulation Solution appeared fi...
May 13, 2021
By Calibre Design Staff Prior to the availability of extreme ultraviolet (EUV) lithography, multi-patterning provided… The post A SAMPle of what you need to know about SAMP technology appeared first on Design with Calibre....

featured video

Industry’s First USB4 Silicon Success

Sponsored by Synopsys

USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.

Click here for more information about DesignWare USB4 IP

featured paper

Keys to quick success using high-speed data converters

Sponsored by Texas Instruments

Hardware designers using modern high-speed data converters face tough challenges. Issues might include connecting with your field-programmable gate array (FPGAs), being confident that your first design pass will work, or determining how to best model the system before building it. In this article, Texas Instruments takes a closer look at each of these challenges.

Click to read more

featured chalk talk

In-Chip Sensing and PVT Monitoring

Sponsored by Synopsys

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Click here for more information about in-chip monitoring and sensing