Part of the Cadence Allegro release features a new field solver they’ve included for power delivery network (PDN) analysis, the product of collaboration with the University of Illinois, Urbana-Champaign. It’s actually integrated with the PCB editor so that analysis and re-editing can be done without having to swap tools.

We covered field solver technology some time ago, but the target applications we focused on there were for on-chip parasitic extraction or package/chip interactions. So I asked whether this was also a target for the new technology being used in Allegro.

The response was that it is likely that it will migrate from the PC board to the package, but not to the chip. While, presumably, the underlying mathematics could be shared, they claim that the product is tailored enough around the materials and structures found in PC boards (and, at some point, packages) that it doesn’t translate easily to on-chip analysis.