Data Center Duel Deux

Intel and Xilinx Take More Turf

by Kevin Morris

It’s clear that programmable logic and FPGA technology will capture an increasing share of the value in conventional and cloud data-center deployments. While FPGAs have always been used in connectivity and storage, there is an ever-building push to have high-end FPGAs take over a crucial role in computation as well. FPGAs pack a potent combination of massive computational throughput, low latency, and power efficiency that is unmatched by any rival technology. With the huge growth of data-center demand fueled by IoT, continuing to power the cloud exclusively with conventional processors is just not feasible. Heterogeneous deployments of conventional processors and FPGAs working together have the potential to boost computational performance many times over and, more importantly, dramatically cut power consumption.  Read More


latest news

March 28, 2017

efabless, X-FAB Announce Results of First Analog-on-Demand Design Challenge

Pentek’s Jade Architecture Module for Wideband Signal Capture and Generation Now Available

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March 27, 2017

Pentek’s Jade Architecture Module for Wideband Signal Capture and Generation Now Available

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March 23, 2017

DDC-I and Logicircuit to Deliver Enhanced DO-178C and DO-254 Support for Xilinx All Programmable Devices

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March 22, 2017

STMicroelectronics Launches Digital Multiphase Controllers for Energy-Efficient Power Delivery in Servers and Data Centers

High-performance, high-bandwidth IP platform for Samsung 14LPP process technology

March 21, 2017

Synopsys Announces Availability of Comprehensive Low Power Reference Kit for Design and Verification

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March 20, 2017

Synopsys Releases LightTools 8.5 with New Tools to Increase Illumination Optical System Efficiency and Performance

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FPGA News Archive

Cypress Tames Two-Headed Monster

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FPGA Article Archive

 

Editors' Blog

A More Secure Time Server

posted by Bryon Moyer

Time servers allow us to track multiple events from different systems and networks with a consistent time base. But an evildoer can flood such servers with requests, causing crashes. Microsemi has released a new time server that addresses this vulnerability. (13-Jan)

QuickLogic Goes Full SoC for Sensors

posted by Bryon Moyer

QuickLogic has announced a new device that builds on ArcticLink, intended to act as the always-on manager for phones and wearables. (30-Jul)

Rumors Intel Altera Deal is Close

posted by Kevin Morris

The NY Post reported today that sources told them that an Intel/Altera deal was close, and could be done by the end of next week. At the same time, we are hearing from multiple Altera customers who are opposed to the deal. (28-May)

Intel/Altera Agreement (Partially) Tells the Tale

posted by Kevin Morris

We did a lot of speculation in our recent articles about the rumored Intel bid to buy Altera. One of the areas of most intense speculation was the 2013 agreement the two companies signed - for Intel to manufacture 14nm FPGAs for Altera. More than two years after that deal was signed, Intel is rumored to be making an offer to buy Altera for upwards (maybe far upwards) of $10B. But, is the existing 2013 agreement potentially weakening Intel’s bargaining position? (4-May)

Intel Altera Deal Off?

posted by Kevin Morris

Multiple financial news sources are reporting today that talks between Intel and Altera have ended... (9-Apr)

FPGA Editors' Blog Archive

 

forum

A New IC Design Model

Posted on 03/29/17 at 3:45 PM by Nanette

Bryon – First of all, let me applaud you for a very thoughtful and very timely article! We closed the first design challenge on your publication date and announce the winners March 28.

There are a few items for fact correction (e.g. 88 designers in th…

Data Center Duel Deux

Posted on 03/29/17 at 9:44 AM by StephaneM

Good analysis Kevin.
Indeed Altera OpenCL and Xilinx SDAccel are a step in the right direction. Experience shows that this model of computation is applicable nicely to a certain type of processing workload but that, for a large portion of Cloud workloads…

Data Center Duel Deux

Posted on 03/28/17 at 1:34 PM by beercandyman

The biggest problem with using FPGA tools is the time it takes to place and route. It's interesting that Xilinx and Intel want you to compile your software into hardware but they won't even try and accelerate their place and route tools. A long time ago X…

EUV as Pizza

Posted on 03/27/17 at 10:37 AM by bmoyer

bmoyer
What do you think about the EUV progress made over the last year?

FPGA Forum Archive

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