Radio FPGA!

Xilinx Announces RFSoCs

by Kevin Morris

CQ CQ CQ - Calling CQ. This is 5G calling...

We’ve all heard it. 5G is coming. Maybe not soon, but as soon as we can get all those pesky technical issues worked out. Which pesky technical issues would those be? Glad you asked. It turns out that cramming a previously unfathomable amount of bandwidth over an unprecedented number of individual connections into each and every cell tower using millimeter wavelengths and 2 dimensional massive multiple-input multiple-output (MIMO) antenna arrays - and doing all of that within acceptable power and footprint constraints - is a really tough problem. Actually, it’s a LOT of really tough problems.  Read More


latest news

February 22, 2017

Lattice Semiconductor Expands CrossLink Programmable ASSP (pASSP) IP Solutions

Xilinx Unveils Disruptive Integration and Architectural Breakthrough for 5G Wireless with RF-Class Analog Technology

February 21, 2017

GLOBALFOUNDRIES Announces Availability of 45nm RF SOI to Advance 5G Mobile Communications

Synopsys IC Compiler II Sets the Bar in Quality-of-Results

DDC-I Announces SafeMC RTOS Technology on Xilinx Zynq UltraScale+ MPSoC Multicore Devices

February 16, 2017

Mentor Graphics Announces Veloce Strato Platform Scales Up to 15BG

February 13, 2017

VadaTech launches MTCA chassis for processing-rich and high-bandwidth applications

GLOBALFOUNDRIES Expands to Meet Worldwide Customer Demand

February 09, 2017

100V No-Opto Flyback Regulator Delivers 5 Watts in SOT-23 Package & Operates at 150°C

February 08, 2017

DVCon U.S. 2017 – Don’t Miss It!

40A Scalable µModule Regulator Protects Load by Tripping Upstream Power Source

February 06, 2017

Optimized for debugging and testing complex high-end SoCs: PLS' UDE 4.8 simplifies trace analysis and the evaluation of runtime behavior of embedded systems

February 01, 2017

Mouser Electronics Introduces Scope Search to Enhance Navigation on Its Industry-Leading Website

Cavium Deploys the Cadence Palladium Z1 Enterprise Emulation Platform

300MHz to 6GHz Dual Wideband Mixer with Programmable Gain Amplifiers Enables 5G Wireless Access

FPGA News Archive

FPGAs Race for the Bottom

Intel, Microsemi Debut New Families

by Kevin Morris

Calling All Cores!

Standards, Tools, and Solving the Multi-Core Heterogeneous Computing Software Conundrum

by Amelia Dalton

How Does Scatter/Gather Work?

Promises of Single-Cycle Access Are True, But…

by Bryon Moyer

What Part of the Elephant Do You Recognise?

National Instruments Passes an Historic Milestone

by Dick Selwood

FPGA Article Archive

 

Editors' Blog

A More Secure Time Server

posted by Bryon Moyer

Time servers allow us to track multiple events from different systems and networks with a consistent time base. But an evildoer can flood such servers with requests, causing crashes. Microsemi has released a new time server that addresses this vulnerability. (13-Jan)

QuickLogic Goes Full SoC for Sensors

posted by Bryon Moyer

QuickLogic has announced a new device that builds on ArcticLink, intended to act as the always-on manager for phones and wearables. (30-Jul)

Rumors Intel Altera Deal is Close

posted by Kevin Morris

The NY Post reported today that sources told them that an Intel/Altera deal was close, and could be done by the end of next week. At the same time, we are hearing from multiple Altera customers who are opposed to the deal. (28-May)

Intel/Altera Agreement (Partially) Tells the Tale

posted by Kevin Morris

We did a lot of speculation in our recent articles about the rumored Intel bid to buy Altera. One of the areas of most intense speculation was the 2013 agreement the two companies signed - for Intel to manufacture 14nm FPGAs for Altera. More than two years after that deal was signed, Intel is rumored to be making an offer to buy Altera for upwards (maybe far upwards) of $10B. But, is the existing 2013 agreement potentially weakening Intel’s bargaining position? (4-May)

Intel Altera Deal Off?

posted by Kevin Morris

Multiple financial news sources are reporting today that talks between Intel and Altera have ended... (9-Apr)

FPGA Editors' Blog Archive

 

forum

FPGAs Race for the Bottom

Posted on 02/20/17 at 4:42 PM by logos

CyrilJ,

You're links are broken.

Also, Microsemi's THREE separate software suites are INCONSISTENT with Linux support.
- FlashPro for Libero IDE does not support Linux. Microsemi's site and documentation is all over the place with FlashPro hardware…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 2:13 PM by TotallyLost

TotallyLost
What is FAR worse?

An 8-way time division multiplexor to "fairly share" memory between 6 processors and 2 DMA channels -- no priority accesses to starve another channel, no contention based allocations, just straight channel 1 gets only time slot 1, ch…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 1:16 PM by TotallyLost

TotallyLost
Now you might say that no one would be that stupid as to pack all accessed data into a single subchannel. With the number of sub-channels being 2^n (where n is 1, 2 or 3), it's also pretty likely that the underlying data structure to be processed will hav…

How Does Scatter/Gather Work?

Posted on 02/20/17 at 12:37 PM by TotallyLost

TotallyLost
@Karl -- sure multiple banks/channels can offer concurrent read/write, or even multiply sourced reads/write -- but each channel still has the native single access or burst fill performance timings.

Now look at the last three figures above, where Cadenc…

FPGA Forum Archive

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