Verifying Your Awesomeness

The Mire of Modern System Verification

by Kevin Morris

If a clock tree fails in a forest, and there are no vectors to catch it…

Verification has always been the black sheep of the engineering family, and for understandable reasons. Design teams are made up of intelligent, capable, and - dare we say occasionally arrogant - types who don’t take kindly to the notion that their work contains errors. Yet, we have verification teams who make their entire career finding the bugs in the work of designers.

Does this sound like a recipe for peace and harmony?

As system complexity has exploded, design productivity has largely kept pace. There is, of course, the ubiquitous EDA marketing slide - a graph over time showing an expanding “gap” between the number of gates we can design and the number of gates Moore’s Law will allow us to put on a chip.  Read More


latest news

January 22, 2015

Negative Input (-4.5V to -80V) Synchronous Buck-Boost/Inverting DC/DC Controller Delivers up to 20A Output Current

January 21, 2015

Five Output Ultralow Jitter Clock Distributor with PLL Provides Unique Multichip Output Synchronization Method

January 20, 2015

Avnet Outlines Key Drivers for 2015 Global Supply Chain

Flexible FPGA Chip with Integrated AFDX Protocol Available from MEN Micro

Telesoft Technologies Selects Achronix Speedster22i FPGAs for Dual 100GbE MPAC6200

January 19, 2015

Avnet Joins OpenPOWER Foundation

Aldec Delivers Unprecedented Scalability and Verification Acceleration with the Latest Release of HES-DVM™

January 16, 2015

Xilinx SDAccel Development Environment for OpenCL, C, and C++, Achieves Khronos Conformance

January 14, 2015

Byte Paradigm announces 'Yugo Systems' solutions dedicated to FPGA Debug.

January 13, 2015

PLDA and M31 Technology Combine PCIe 3.0 Controller and PHY for a Complete, Reliable ASIC Design Solution

January 12, 2015

Keysight Technologies Expands Use of its FPGA Development Kit for Full Range of High-Speed Digitizers

January 08, 2015

Avnet Electronics Marketing Releases WiLink 8 Wi-Fi, Bluetooth and Bluetooth Low Energy Pmod Adaptor

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January 06, 2015

GUC and Credo Collaborate to Enable 16-nm FinFET+ Chip Development

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Editors' Blog

On the Scene: Almost-Instant Semi Quotes with eSilicon

posted by Amelia Dalton

Good night red tape. Online Semi quotes made easy with eSilicon (8-Dec)

QuickLogic’s Next Sensor Hub Rev

posted by Bryon Moyer

QuickLogic released a new version of their ArcticLink 3 sensor hub (7-Oct)

QuickLogic Goes Wearable

posted by Bryon Moyer

QuickLogic has announced a wearable version of their sensor hub technology. How much does it differ from what we’ve seen in the past from them? (24-Jul)

Improved FPGA Tool Results

posted by Bryon Moyer

Plunify tries to get the best out of FPGA design tools (21-Jul)

On the Scene: Project Ara

posted by Amelia Dalton

The race hasn't yet begun. In fact, we're not even on the starting block, but the rule book for this race - the race to the next major innovative mobile platform (smartphone) has been drafted and teams are starting to assemble. Google's Project Ara, the world's first completely modular smartphone is coming, and the modules will be designed by... YOU! On your mark. Get set. Design! (21-Apr)

FPGA Editors' Blog Archive

 

forum

Verifying Your Awesomeness

Posted on 01/24/15 at 1:38 AM by Kev

Kev
I would ask the question: what is it that you are verifying?

Digital stuff is all representable as FSMs and it should be possible to make that run fast in simulation and formally verify that the implementation is correct. However, there are lots of ana…

2014 Letdown

Posted on 01/19/15 at 1:21 PM by Dick Selwood

Dick Selwood
Mike
Just shows I have probably been around too long. I meant to type ST. But the back of my mind was SGS Thomson. How long ago did they change the name? Just checked- only 17 years ago

EDA for SETs

Posted on 01/19/15 at 9:26 AM by bmoyer

bmoyer
What do you think of this algorithmic approach to fitting logic into single-electron transistor fabrics?

2014 Letdown

Posted on 01/16/15 at 4:24 PM by MikeB

"While the rest of the world seems to accept that three-dimensional or FinFET technology is the only way to keep up with Moore's Law, SGS seems to be making steady progress ..."

Well spotted on noting it's two companies sharing the same HQ, but it's Th…

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