Programmability for the People

Xilinx Kicks Up Cost-Optimized Offering

by Kevin Morris

It’s always fun to fantasize about Ferraris and FinFETs. After all, what true engineer doesn’t get a little tingly talking about terabits of bandwidth, single-digit nanometers, and gazillions of LUTs. But, in practical terms, the vast majority of us don’t have an actual application need for the biggest, fastest FPGAs and SoCs on the market. And, while it’s fun to watch and speculate about which company can cram the most transistors onto an integrated circuit, the reality is that, for most of us, our actual requirements are much more modest.

Fortunately, the programmable logic companies realize this, and, in the midst of all the marketing bravado and chest beating about the new high-end FPGA families, Xilinx is announcing a major upgrade to their non-bleeding-edge families - Zynq, Artix, and - back by popular demand - Spartan.  Read More


latest news

September 28, 2016

100MHz to 40GHz RMS Power Detector Offers 1dB Accuracy & 35dB Dynamic Range

Xilinx Extends its Cost-Optimized Portfolio Targeting a Wide Range of Applications Including Embedded Vision and Industrial IoT

September 27, 2016

Imagination licenses UltraSoC IP to deliver system-level debug and optimization capabilities for SoCs

September 26, 2016

Pentek Introduces Evolutionary Jade Architecture with Navigator Design Suite Software Tools

September 23, 2016

TSMC and Synopsys Collaboration Delivers Innovative Technologies for the High Performance Compute (HPC) Platform

Cadence and TSMC Advance 7nm FinFET Designs for Mobile and HPC Platforms

September 22, 2016

Avnet and Arizona State University Seek Nation’s Next Technology Entrepreneurs

40VIN, 2.1A Rail-to-Rail LDO+ Now Offered in High Temp, 150°C H-Grade in TSSOP Package

September 21, 2016

eSilicon revolutionizes semiconductor IP selection and purchasing

Synopsys and TSMC Collaborate to Certify Custom Compiler for 16FFC Process

Altium CircuitStudio v1.2 now available exclusively from element14 via eDelivery

Mentor Graphics Extends Offering to Support TSMC 7nm and 16FFC FinFET Process Technologies

Dual µModule Regulator in 15mm x 9mm x 2.42mm BGA is Configurable as SEPIC (Buck-Boost) and Inverting

September 20, 2016

Real Intent Sets a New Benchmark in Early Verification of Digital Designs with Release 2016.A of Ascent Lint

UltraSoC supports RISC-V: “the Linux of the semiconductor industry”

FPGA News Archive

Xilinx vs Intel

The New Showdown in Programmable Logic

by Kevin Morris

Xilinx Tackles the "Diagonal”

Winning at FPGA is a Complex Business

by Kevin Morris

Intel’s First FPGAs

Altera Turns a Page

by Kevin Morris

The Quiet FPGAs

Microsemi Soldiers On Silently

by Kevin Morris

FPGA Article Archive

 

Editors' Blog

A More Secure Time Server

posted by Bryon Moyer

Time servers allow us to track multiple events from different systems and networks with a consistent time base. But an evildoer can flood such servers with requests, causing crashes. Microsemi has released a new time server that addresses this vulnerability. (13-Jan)

QuickLogic Goes Full SoC for Sensors

posted by Bryon Moyer

QuickLogic has announced a new device that builds on ArcticLink, intended to act as the always-on manager for phones and wearables. (30-Jul)

Rumors Intel Altera Deal is Close

posted by Kevin Morris

The NY Post reported today that sources told them that an Intel/Altera deal was close, and could be done by the end of next week. At the same time, we are hearing from multiple Altera customers who are opposed to the deal. (28-May)

Intel/Altera Agreement (Partially) Tells the Tale

posted by Kevin Morris

We did a lot of speculation in our recent articles about the rumored Intel bid to buy Altera. One of the areas of most intense speculation was the 2013 agreement the two companies signed - for Intel to manufacture 14nm FPGAs for Altera. More than two years after that deal was signed, Intel is rumored to be making an offer to buy Altera for upwards (maybe far upwards) of $10B. But, is the existing 2013 agreement potentially weakening Intel’s bargaining position? (4-May)

Intel Altera Deal Off?

posted by Kevin Morris

Multiple financial news sources are reporting today that talks between Intel and Altera have ended... (9-Apr)

FPGA Editors' Blog Archive

 

forum

Xilinx vs Intel

Posted on 09/28/16 at 12:53 AM by rcousins

Hey Kevin, I was kind of surprised you didn't throw Xilinx's SDSoC into the conversation - not that it's some kind of magic wand/potion, but I'd be interested to hear your thoughts on the tool as it pertains to the C/C++ --> HDL 'dream'... I seem to vague…

Abstracting Register Sequences

Posted on 09/26/16 at 11:34 AM by bmoyer

bmoyer
What do you think of Agnisys's approach to register sequence specification?

Intel’s First FPGAs

Posted on 09/24/16 at 12:23 PM by KarlS51

It is about time to quit building things from such tiny pieces such as wiring segments and single FFs as that requires too much P&R.

CPUs have been using microcode for generations and many features and bug fixes have been done just with new microcode.

Intel’s First FPGAs

Posted on 09/21/16 at 12:45 AM by TotallyLost

TotallyLost
HLL to gates at the 95% level is much easier than one might guess ... although there are parts of some HLL's that do not map well (dynamic allocation in C++ and JAVA, arbitrary pointers in C, etc). I spent a few years at that problem with FpgaC, and made …

FPGA Forum Archive

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