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Moving Between FPGA and ASIC with High-Level Synthesis


Writing RTL that works smoothly on both FPGA and ASIC implementations is nearly impossible.
But, High-Level Synthesis (HLS) can make technology-independent design a breeze. In this episode of Chalk Talk, Amelia Dalton chats with Stuart Clubb of Mentor’s Catapult team about how to use HLS to accelerate your design flow.

Click here for more information about Catapult® High-Level Synthesis

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