MOUNTAIN VIEW, Calif., March 12, 2015 /PRNewswire/ — Synopsys, Inc. (NASDAQ: SNPS) announces the availability of verification IP (VIP) for the MIPI® Alliance SoundWireSM 1.0 specification. Synopsys VIP for MIPI SoundWire is based on a native SystemVerilog UVM architecture to enable IP, subsystem and system-on-chip (SoC) designers to easily integrate their designs and accelerate verification performance. Synopsys VIP for MIPI SoundWire also includes SystemVerilog source code test suites to eliminate the tasks of developing a verification environment and the required tests. Complete with verification plans, built-in coverage and support for protocol-aware debug, Synopsys VIP for MIPI SoundWire accelerates verification closure for designers of low power audio and control interfaces used in mobile and mobile-influenced devices.
“MIPI SoundWire consolidates many of the key attributes available in mobile and PC industry audio interfaces and introduces a scalable, low power, two-pin multi-drop architecture that can be used to transport multiple audio streams along with embedded controls and commands,” said Joel Huloux, chairman of the board of MIPI Alliance. “The release of Synopsys VIP for MIPI SoundWire strengthens the ecosystem, required to facilitate early adoption and fast development of MIPI SoundWire-based designs.”
“As an active contributing member of the MIPI Alliance, we have collaborated closely with all working groups to develop VIP that allows leading-edge SoC design teams to address the increasingly demanding process of protocol compliance verification; this accelerates verification closure and time to market for mobile and mobile-influenced devices,” said Debashis Chowdhury, vice president of R&D for the Synopsys Verification Group. “The release of the Synopsys VIP for MIPI SoundWire underscores our continued investment in our VIP portfolio to enable increased design quality and faster, more complete verification closure.”
Availability
Synopsys VIP for MIPI SoundWire is available standalone today, as well as being included in the Synopsys VIP Library and the Verification Compiler™ products.
About Synopsys Verification IP
Synopsys VIP, based on its next-generation architecture and implemented in native SystemVerilog, offers native performance, native debug with Verdi® Protocol Analyzer, enhanced VIP ease of use, configurability, coverage and source code compliance test suites. These capabilities substantially increase user productivity for one of the most difficult and time-consuming aspects of SoC design and verification. The Synopsys VIP library includes a broad portfolio of interface, bus, and memory protocols. More information is available at www.synopsys.com/vip.
About Synopsys
Synopsys, Inc. (Nasdaq:SNPS) is the Silicon to Software™ partner for innovative companies developing the electronic products and software applications we rely on every day. As the world’s 15th largest software company, Synopsys has a long history of being a global leader in electronic design automation (EDA) and semiconductor IP, and is also a leader in software quality and security testing with its Coverity® solutions. Whether you’re a system-on-chip (SoC) designer creating advanced semiconductors, or a software developer writing applications that require the highest quality and security, Synopsys has the solutions needed to deliver innovative, high-quality, secure products. Learn more at www.synopsys.com.
