Learn about maskless electron beam lithography and see how Multibeam's industry-first e-beam semiconductor lithography system leverages Synopsys software.

We explore Aerospace and Government (A&G) chip design and explain how Silicon Lifecycle Management (SLM) ensures semiconductor reliability for A&G applications.

Learn what gate-all-around (GAA) transistors are, explore the switch from fin field-effect transistors (FinFETs), and see the impact on SoC design & EDA tools.

See how Cisco accelerates library characterization and chip design with our cloud EDA tools, scaling access to SoC validation solutions and compute services.

Learn what IR Drop is, explore the chip design tools and techniques involved in power network analysis, and see how it accelerates the IC design flow.

See how Achronix used our physical verification tools to accelerate the SoC design and verification flow, boosting chip design productivity w/ cloud-based EDA.

Learn how we're working with PCI-SIG to transition PCIe to optical interfaces and explore our demo of the PCIe 7.0 standard over fiber optics with OpenLight.

Explore the impact of AI-powered EDA tools on semiconductor design with key takeaways from our AI-driven chip design panel at SNUG Silicon Valley 2024.

See how Mentium designed and taped out their AI accelerator chip, created for use in deep space with NASA, using our SaaS cloud EDA tools and IP resources.

CEO Sassine Ghazi explains how AI, silicon, and software-defined systems fuel innovation in the era of pervasive intelligence, at SNUG Silicon Valley 2024.

We're tackling the tech talent shortage by expanding STEM education through university partnerships, engineering internships, and joint curriculum development.

Learn how we're providing semiconductor training through workforce development programs, addressing the semiconductor labor shortage around the world.

In this episode of Chalk Talk, Amelia Dalton and Guy Cortez from Synopsys investigate how Synopsys’ Silicon.da platform can increase engineering productivity and silicon efficiency while providing the tool scalability needed for today’s semiconductor designs. They also walk through the steps involved in a SLM workflow and examine how this open and extensible platform can help you avoid pitfalls in each step of your next IC design.

The adoption of the cloud in the design automation industry has encouraged innovation across the entire semiconductor lifecycle. In this episode of Chalk Talk, Amelia Dalton chats with Vikram Bhatia from Synopsys about how Synopsys is redefining EDA in the Cloud with the industry’s first complete browser-based EDA-as-a-Service cloud platform. They explore the benefits that this on-demand pay-per use, web-based portal can bring to your next design. 

Benchmarking is a great way to measure the performance of computing resources, but benchmark tuning can be a very complicated problem to solve. In this episode of Chalk Talk, Nozar Nozarian from Synopsys and Amelia Dalton investigate Synopsys’ Optimizer Studio that combines an evolution search algorithm with a powerful user interface that can help you quickly setup and run benchmarking experiments with much less effort and time than ever before.

In order to keep up with the rigorous pace of today’s electronic designs, we must have visibility into each step of our IC design lifecycle including debug, bring up and in-field operation. In this episode of Chalk Talk, Amelia Dalton chats with Steve Pateras from Synopsys about in-field infrastructure for silicon lifecycle management, the role that edge analytics play when it comes to in-field optimization, and how cloud analytics, runtime agents and SiliconMAX sensor analytics can provide you more information than ever before for the lifecycle of your IC design.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Award-winning Synopsys.ai, the industry’s first full stack, AI-driven electronic design automation suite, offers AI-driven workflow optimization & data analytics solutions along with breakthrough generative AI capabilities for next-level chip design.

This whitepaper explains the basics of UVM functional coverage for RISC-V cores using the Google RISCV-DV open-source project, Synopsys verification solutions, and a RISC-V processor core from Bluespec.

Adding safety measures to SoC designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the A&D, cloud, automotive, robotics, medical, and IoT industries more resilient against random hardware failures that occur. This paper discusses the automated process of implementing the safety mechanisms/measures (SM) in the design to make them more resilient and analyze their effectiveness from design inception to the final product.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

Aerospace, Government, and Defense industry experts discuss the complexities of 3DHI for technological, manufacturing, & economic intricacies, as well as security, reliability, and safety challenges & solutions. Explore DARPA’s NGMM plan for the 3DHI R&D ecosystem.

Synopsys ARC-V™ Processor IP delivers the optimal power-performance-efficiency and extensibility of ARC processors with broad software and tools support from Synopsys and the expanding RISC-V ecosystem. Built on the success of multiple generations of ARC processor IP covering a broad range of processor implementations, including functional safety (FS) versions, the ARC-V portfolio delivers what you need to optimize and differentiate your SoC.

Join Gary Ruggles, Synopsys Product Manager for PCIe & CXL, at PCI-SIG DevCon 2023 and see Synopsys PCIe 6.0 Controller & PHY IP in an end-to-end host to device system, using Teledyne LeCroy's interposer & analyzer showing impact of payload size on throughput.

See successful PCIe 6.0 interoperability demos in our booth & our partners’ booths at PCI-SIG DevCon 2023. Don’t miss our demo at 128 GT/s as we take a peek into the PCIe 7.0 tech and make sure to watch the world’s first PCIe 6.0 RX link training compliance tests.

At TSMC Symposium 2023 we showcased a successful 224G Ethernet PHY IP interop demonstration with backplane channels. Watch the various plots, ADC histogram and excellent eye diagrams results.

Watch this video of Synopsys 224G Ethernet PHY IP demonstrating wide-open TX PAM-4 eyes using Keysight’s oscilloscope & Samtec’s cables and connectors.

As glitch power becomes a growing component of total power, managing it requires a holistic solution for analysis and optimization from architecture to signoff. Watch this video and learn how to minimize glitch power in your designs.

This video shows how IC Compiler II and Fusion Compiler enable intelligent planning and implementation of complex interconnects through innovative Topological Interconnect Planning technology - accelerating schedules and achieving highest QoR.