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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

From Silicon to Software

GIRLS GO Engineering! Empowers Our Next-Gen Women in Tech

The GIRLS GO Engineering scholarship provides opportunities for women in tech and fosters diversity in STEM; see the winners of our 2021 engineering challenge!

Sep 23, 2021
High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1

Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging.

Sep 21, 2021
What’s Driving the Demand for Chiplets?

Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore's Law.

Sep 15, 2021
Q&A with Priyanka Joshi, Women in Semiconductor Hardware (WISH) Conference Paper Presenter

We sat down with intern Priyanka Joshi to discuss low-power, mixed-signal DDR design ahead of the 2021 Women in Semiconductor Hardware (WISH) conference.

Sep 13, 2021
Providing University Students with Real-World Chip Design Experience

Our Electronic Design University Program gives students access to the latest IC design & EDA tools, fostering the next generation of chip design engineers.

Sep 9, 2021
Sharpen Your Silicon Design Expertise at Synopsys Events this Fall

Fall 2021 silicon design events are almost here! Join us for ARC Processor Virtual Summit, Verification Day 2021, and the Digital Design Technology Symposium.

Sep 7, 2021
AI Is Designing AI Chips: What’s Next? Find Out at AI Hardware Summit 2021

Join us at AI Hardware Summit 2021 for technical sessions on tools & advancements in AI chips, SoC design, deep learning acceleration, and AI architectures.

Sep 2, 2021
What Are Key ISO 26262 Functional Safety Challenges for Automotive Design and Verification Teams?

We explain ISO 26262 and automotive functional safety certification challenges, from finding design failures to avoiding bugs in functional safety mechanisms.

Sep 1, 2021
4 Key Considerations When Evaluating EDA in the Cloud

We share 4 key criteria for evaluating cloud-based EDA tools, including cloud security and data migration, which enhance silicon design & chip verification.

Aug 26, 2021
Beyond Machine Learning and Homomorphic Encryption: Why Advanced Verification Is Key to Fueling a New Era of AI Chips

Learn how advanced SoC verification (equivalence checking) & SoC security (homomorphic encryption) technologies help chip designers create specialized AI chips.

Aug 25, 2021
Top 5 Electric Vehicle Design Challenges

We explore EV design challenges such as range & charging infrastructure, and explain how to improve electric vehicle safety & reliability with robust design.

Aug 24, 2021
Will Autonomous Chip Design Take Your Job Away?

Ahead of Hot Chips 2021 we explain the rise of AI chip design tools, which are helping chip designers create larger, more complex & more efficient chip designs.

Aug 19, 2021

Read more from the Synopsys Silicon to Software blog…

 

Chalk Talks Featuring Synopsys

Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
21,073 views
In-Chip Sensing and PVT Monitoring
In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.
Mar 19, 2021
23,910 views
Silicon Lifecycle Management (SLM)
Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.
Feb 25, 2021
26,497 views
Accelerating Physical Verification Productivity Part Two
Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 
Jan 27, 2021
29,004 views

 

Synopsys Designer’s Digest

PrimeLib Next-Gen Library Characterization - Providing Accelerated Access to Advanced Process Nodes
What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.
Jul 14, 2021

 

Featured Videos from Synopsys

Digital Design Technology Symposium
Are you an SoC designer or manager facing new design challenges driven by rapidly growing and emerging vertical segments for HPC, 5G, mobile, automotive and AI applications?
Sep 21, 2021
2,513 views
Silicon Lifecycle Management Paradigm Shift
An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.
Sep 21, 2021
2,587 views
Product Update: Complete DesignWare 400G/800G Ethernet IP
In this video product experts describe how designers can maximize the performance of their high-performance computing, AI and networking SoCs with Synopsys' complete DesignWare Ethernet 400G/800G IP solution, including MAC, PCS and PHY.
Sep 16, 2021
6,594 views
ARC® Processor Virtual Summit 2021
Designing an embedded SoC? Attend the ARC Processor Virtual Summit on Sept 21-22 to get in-depth information from industry leaders on the latest ARC processor IP and related hardware and software technologies that enable you to achieve differentiation in your chip or system design.
Aug 31, 2021
19,625 views
Accelerate Intelligent SLAM with DesignWare ARC EV Processor IP
Simultaneous localization and mapping (SLAM) algorithms build a map and determine location in the map at the same time. But how can you speed up the results? This demo shows how ARC EV processor IP with CNN engine accelerates KudanSLAM algorithms.
Jul 30, 2021
25,666 views
Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP
Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.
Jul 30, 2021
26,193 views
Design Success with Foundation IP & Fusion Compiler
When is 1+1 greater than 2? When using DesignWare Foundation IP & Fusion Compiler! Join Raymond and Yung in their discussion of a customer that benefited from the combination of Fusion Compiler’s machine learning and Foundation IP cells and macros.
Jul 7, 2021
26,133 views
DesignWare Controller and PHY IP for PCIe 6.0
See a demo of Synopsys’ complete IP solution for PCIe 6.0 technology showing the controller operating at 64GT/s in FLIT mode and the PAM-4 PHY in 5-nm process achieving two orders of magnitude better BER with 32dB PCIe channel.
Jul 6, 2021
25,755 views