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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

From Silicon to Software – Latest Posts

The Importance of Chip Manufacturing & Test Data Analytics in the Semiconductor Industry

Data & analytics have a massive impact on the chip design process; we explore how fast/precise chip data analytics solutions improve IC design quality & yield.

Jun 10, 2021
Approximating Silicon with Scaled-Out FPGA Prototyping Farms

We explore the advantages of FPGA prototyping in the chip design process, as ASICs trend towards multi-billion gate designs for AI, machine learning & beyond.

Jun 9, 2021
How to Achieve High Bandwidth and Low Latency Die-to-Die Connectivity

Die-to-die interfaces in hyperscale data centers require high bandwidth & low latency, learn how this innovation drives modern high-performance computing (HPC).

Jun 3, 2021
Customer Spotlight: Tachyum’s Universal Processor for Hyperscale Data Centers

Synopsys customer Tachyum's new Prodigy processor is set to transform hyperscale data centers, making AI & high-performance computing (HPC) more accessible.

Jun 1, 2021
How ISO/SAE 21434 Impacts EDA and IP Vendors

We explain the automotive cybersecurity framework of ISO/SAE 21434, and how IP & EDA tools help designers build security into automotive SoCs & sensors.

May 27, 2021
Arm Collaboration Helps You Meet PPA Targets Faster for AI, Cloud, and 5G Infrastructure Chiplets

Explore our collaboration with Arm and learn how our EDA tools help you design chiplets and SoCs while meeting aggressive PPA and time-to-market targets.

May 26, 2021
Why It’s Critical to Design in Security Early to Protect Automotive Systems from Hackers

Learn why ECUs & In-Vehicle Networks are critical to automotive cybersecurity, and explore the NHTSA's best practices including automotive ethernet security.

May 20, 2021
Why Hyper-Convergent Designs Demand an All or Nothing Approach

We explain the importance of hyper-convergent-friendly chip design tools for larger, more complex IC designs powering HPC & advanced software infrastructure.

May 19, 2021
Synopsys Makes Headlines with PrimeSim Continuum, an Innovative Circuit Simulation Solution

Our new IC design tool, PrimeSim Continuum, enables the next generation of hyper-convergent IC designs. Learn more from eeNews, Electronic Design & EE Times.

May 13, 2021
Q&A with Dr. Renu Mehra of Synopsys Digital Design Group: Pioneering Automated Power Management Technologies for Chip Design

We discuss low power design with Dr. Renu Mehra, R&D group director in our Digital Design Group, along with her career in STEM & the future of RTL synthesis.

May 12, 2021
Find Bugs Earlier Via On-the-Fly Code Checking for Productive Chip Design and Verification

Learn how correct-by-construction coding enables a more productive chip design process, as new code review tools address bugs early in the design process.

May 6, 2021
How 5G Networks Will Accelerate Development of Smart Cities

New 5G infrastructure is powering smart city projects worldwide; explore the importance of IoT security for smart city solutions in public safety & logistics.

May 5, 2021

Read more from the Synopsys Silicon to Software blog…

 

Latest Featured Content from Synopsys

featured video
Kyocera Super Resolution Printer with ARC EV Vision IP
See the amazing image processing features that Kyocera’s TASKalfa 3554ci brings to their customers.
Jun 3, 2021
6,636 views
featured video
Industry’s First USB4 Silicon Success
USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.
May 14, 2021
23,322 views
featured video
What’s Hot: DesignWare Logic Library IP for TSMC N5
Designing for N5? Josefina Hobbs details the latest info and customer results on Logic Library IP for TSMC N5. Whether performance, power, area or routability are your key concerns, Synopsys Library IP helps you meet your toughest design challenges.
May 14, 2021
22,804 views
featured video
Super Resolution with ARC EV Processor IP
Interested in upscaling images with AI? Join Gordon Cooper for an update on SR-GAN with ARC EV Processors.
May 14, 2021
22,636 views

 

Chalk Talks Featuring Synopsys

Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
8,064 views
In-Chip Sensing and PVT Monitoring
In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.
Mar 19, 2021
11,218 views
Silicon Lifecycle Management (SLM)
Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.
Feb 25, 2021
14,268 views
Accelerating Physical Verification Productivity Part Two
Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 
Click here for more information about Physical Verification using IC Validator
Jan 27, 2021
17,736 views

 

Featured Videos from Synopsys

Kyocera Super Resolution Printer with ARC EV Vision IP
See the amazing image processing features that Kyocera’s TASKalfa 3554ci brings to their customers.
Jun 3, 2021
6,636 views
Industry’s First USB4 Silicon Success
USB4 offers up to 40Gbps speeds for incredibly fast connections. Join Synopsys to see the first demonstration of USB4 IP in silicon, along with real TX eyes for DesignWare USB4, DisplayPort, and USB 3.x IP.
May 14, 2021
23,322 views
What’s Hot: DesignWare Logic Library IP for TSMC N5
Designing for N5? Josefina Hobbs details the latest info and customer results on Logic Library IP for TSMC N5. Whether performance, power, area or routability are your key concerns, Synopsys Library IP helps you meet your toughest design challenges.
May 14, 2021
22,804 views
Super Resolution with ARC EV Processor IP
Interested in upscaling images with AI? Join Gordon Cooper for an update on SR-GAN with ARC EV Processors.
May 14, 2021
22,636 views
Insights on StarRC Standalone Netlist Reducer
With the ever-growing size of extracted netlists, parasitic optimization is key to achieve practical simulation run times. Key trade-off for any netlist reducer is accuracy vs netlist size. StarRC Standalone Netlist reducer provides the flexibility to optimize your netlist on a per net basis. The user has total control of trading accuracy of some nets versus netlist optimization - yet another feature from StarRC to provide flexibility to the designer.
May 10, 2021
25,159 views
Meeting Cloud Data Bandwidth Requirements with HPC IP
As people continue to work remotely, demands on cloud data centers have never been higher. Chip designers for high-performance computing (HPC) SoCs are looking to new and innovative IP to meet their bandwidth, capacity, and security needs.
Mar 15, 2021
28,151 views
Silicon-Proven Automotive-Grade DesignWare IP
Get the latest on Synopsys' automotive IP portfolio supporting ISO 26262 functional safety, reliability, and quality management standards, with an available architecture for SoC development and safety management.
Feb 3, 2021
25,000 views
Designing your own Processor with ASIP Designer
Designing your own processor is time-consuming and resource intensive, and it used to be limited to a few experts. But Synopsys’ ASIP Designer tool allows you to design your own specialized processor within your deadline and budget. Watch this video to learn more.
Feb 3, 2021
24,677 views