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Self-driving cars. Machines that learn. Lightning-fast communication across billions of devices in the datasphere. Synopsys technology is at the heart of innovations that are changing the way people work and play in our era of Smart Everything. We provide the world’s most advanced technologies for chip design, verification, IP integration, and software security and quality testing. In short, we help our customers innovate from silicon to software so they can bring Smart Everything to life.

 

From Silicon to Software

Top 5 Challenges to Achieve High-Level Automated Driving

Learn about key roadblocks to improve ADAS systems & higher levels of autonomous driving, such as SoC performance, from our 2021 ARC Processor Virtual Summit.

Oct 19, 2021
HBM3 Will Feed the Growing Need for Speed

High-Bandwidth Memory (HBM) interfaces prevent bottlenecks in online games, AI applications, and more; we explore design challenges and IP solutions for HBM3.

Oct 13, 2021
From Secure Silicon to 3DICs, Synopsys Highlights Innovations at DARPA ERI Summit

We're showcasing chip design & EDA innovations at DARPA's 2021 Electronics Resurgence Initiative (ERI) Summit & MTO Symposium, including 3DICs & SoC emulation.

Oct 12, 2021
High Debug Productivity Is the FPGA Prototyping Game Changer: Part 2

Explore key challenges of performing RTL debug using an FPGA prototyping system, along with game-changing debugging tools for enhanced chip design verification.

Oct 7, 2021
7 Tips for Benchmarking Embedded Processor IP for AI SoCs

Learn how to benchmark AI processors and select the optimal embedded processor IP and neural network accelerator for each AI application's unique requirements.

Oct 6, 2021
Unified Power Format (UPF) and Beyond: How to Expand Low-Power Signoff

We explain how advanced power management techniques including Unified Power Format (UPF) expand low power design techniques and enhance IC design efficiency.

Oct 5, 2021
Empowering Chip Innovation with Hyper-Convergent Chip Design Technologies

Learn how a convergent SoC design flow enables faster, more innovative SoC designs with common data models & machine learning-powered chip design optimizations.

Sep 30, 2021
The Real Impact of AI on Chip Design Is Autonomous Insight

Explore the impact of AI on chip design tools and how increased compute in AI applications enables autonomous design insights from near infinite possibilities.

Sep 29, 2021
A Pioneering Approach to Safety: PrimeSim Reliability Takes Center Stage

Conduct full-lifecycle IC design reliability verification with PrimeSim Reliability Analysis, a chip design tool ensuring safety in SoC and IC applications.

Sep 27, 2021
GIRLS GO Engineering! Empowers Our Next-Gen Women in Tech

The GIRLS GO Engineering scholarship provides opportunities for women in tech and fosters diversity in STEM; see the winners of our 2021 engineering challenge!

Sep 23, 2021
High Debug Productivity Is the FPGA Prototyping Game Changer: Part 1

Learn how our high-performance FPGA prototyping tools enable RTL debug for chip validation teams, eliminating simulation/emulation during hardware debugging.

Sep 21, 2021
What’s Driving the Demand for Chiplets?

Learn how chiplets form the basis of multi-die HPC processor architectures, fueling modern HPC applications and scaling performance & power beyond Moore's Law.

Sep 15, 2021

Read more from the Synopsys Silicon to Software blog…

 

Chalk Talks Featuring Synopsys

Yield Explorer and SiliconDash
Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.
Apr 12, 2021
23,982 views
In-Chip Sensing and PVT Monitoring
In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.
Mar 19, 2021
26,323 views
Silicon Lifecycle Management (SLM)
Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.
Feb 25, 2021
28,982 views
Accelerating Physical Verification Productivity Part Two
Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 
Jan 27, 2021
31,365 views
Accelerating Physical Verification Productivity
Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.
May 29, 2019
53,587 views

 

Synopsys Designer’s Digest

Improving Design Robustness and Efficiency for Today’s Advanced Nodes
Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.
Sep 28, 2021
PrimeLib Next-Gen Library Characterization - Providing Accelerated Access to Advanced Process Nodes
What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.
Jul 14, 2021

 

Featured Videos from Synopsys

Fast & Accurate 3D Object Detection for LiDAR with DesignWare ARC EV Processor IP
This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.
Oct 18, 2021
968 views
DesignCon 2021 112G Ethernet & PCIe 6.0 IP Demos
This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.
Sep 29, 2021
16,187 views
Digital Design Technology Symposium
Are you an SoC designer or manager facing new design challenges driven by rapidly growing and emerging vertical segments for HPC, 5G, mobile, automotive and AI applications?
Sep 21, 2021
22,193 views
Silicon Lifecycle Management Paradigm Shift
An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.
Sep 21, 2021
22,498 views
Product Update: Complete DesignWare 400G/800G Ethernet IP
In this video product experts describe how designers can maximize the performance of their high-performance computing, AI and networking SoCs with Synopsys' complete DesignWare Ethernet 400G/800G IP solution, including MAC, PCS and PHY.
Sep 16, 2021
25,322 views
ARC® Processor Virtual Summit 2021
Designing an embedded SoC? Attend the ARC Processor Virtual Summit on Sept 21-22 to get in-depth information from industry leaders on the latest ARC processor IP and related hardware and software technologies that enable you to achieve differentiation in your chip or system design.
Aug 31, 2021
25,877 views
Accelerate Intelligent SLAM with DesignWare ARC EV Processor IP
Simultaneous localization and mapping (SLAM) algorithms build a map and determine location in the map at the same time. But how can you speed up the results? This demo shows how ARC EV processor IP with CNN engine accelerates KudanSLAM algorithms.
Jul 30, 2021
25,723 views
Vibrant Super Resolution (SR-GAN) with DesignWare ARC EV Processor IP
Super resolution constructs high-res images from low-res. Neural networks like SR-GAN can generate missing data to achieve impressive results. This demo shows SR-GAN running on ARC EV processor IP from Synopsys to generate beautiful images.
Jul 30, 2021
26,403 views