Lean how virtual electronic control units (ECUs) accelerate automotive design and enable advanced driver-assistance systems (ADAS) for connected vehicles.

We explain clock domain crossing & common challenges faced during the ASIC design flow as chip designers scale up CDC verification for multi-billion-gate ASICs.

We explore chip design verification and EDA tools that increase functional verification efficiency to meet coverage goals and find more bugs in less time.

Silicon Lifecycle Management (SLM)'s chip design insights improve design calibration, reduce SoC testing time, and predict/prevent chip failures & attacks.

We explain the growth of High-Performance Computing (HPC) applications and the chip-design advantages of using silicon-proven SoC IP for HPC processor designs.

EDA tools are moving to the cloud; we explore the cost/performance benefits of applying cloud compute resources to formal chip design verification workloads.

Explore how cloud-based FPGA prototyping tools accelerate the SoC design flow, enabling pre-silicon chip validation & easing workflows for shorter time-to-market.

Latha Venkatachari, VP of Applications Engineering, discusses her STEM career path and the importance of diversity in leadership and women in tech jobs.

We explain quantum computing: the role of chip design & photonics, development & deployment challenges, and quantum computing applications & solutions.

Go behind the scenes of Global Impact Day 2021, 24 hours of partnerships and activities focused on giving, acting & sharing in our communities around the world.

Effective SoC verification requires realistic software workloads during full chip power signoff; explore advantages of SoC emulation such as RTL power analysis.

Ethernet bandwidth is in demand for digital media, 5G infrastructure, HPC & more. Learn how the upcoming 1.6T ethernet standard will impact data infrastructure.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Smart speakers and voice-controlled devices are getting better at understanding requests through NLP. This demo shows how ARC VPX DSP Processor IP moves NLP from the cloud to embedded edge devices for lower latency and excellent power efficiency.

This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.

This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.

Are you an SoC designer or manager facing new design challenges driven by rapidly growing and emerging vertical segments for HPC, 5G, mobile, automotive and AI applications?

An end-to-end platform solution, Silicon Lifecycle Management leverages existing, mature, world-class technologies within Synopsys. This exciting new concept will revolutionize the semiconductor industry and how we manage silicon design. For the first time, designers can look inside silicon chip devices from the moment the design is created to the point at which they end their life.

In this video product experts describe how designers can maximize the performance of their high-performance computing, AI and networking SoCs with Synopsys' complete DesignWare Ethernet 400G/800G IP solution, including MAC, PCS and PHY.

Designing an embedded SoC? Attend the ARC Processor Virtual Summit on Sept 21-22 to get in-depth information from industry leaders on the latest ARC processor IP and related hardware and software technologies that enable you to achieve differentiation in your chip or system design.

Simultaneous localization and mapping (SLAM) algorithms build a map and determine location in the map at the same time. But how can you speed up the results? This demo shows how ARC EV processor IP with CNN engine accelerates KudanSLAM algorithms.