High performance computing continues to expand & evolve; our team shares their 2022 HPC predictions including new HPC applications and processor architectures.

Explore the importance of system interoperability in hyperscale data centers and why it matters for AI and high-performance computing (HPC) applications.

Learn how AI-enabled system debug tools accelerate the pre-silicon chip debug process and reduce SoC verification time to shorten chip design turnaround.

See what's behind the boom in AI applications and explore the advanced AI chip design tools and strategies enabling AI SoCs for HPC, healthcare, and more.

5G SoC design is powered by virtual chip verification tools; explore our partnership w/ Keysight and how it accelerates 5G rollout for 5G systems manufacturers.

We share our AI predictions for 2022, including the impact of AI on SoC design and security, trending AI applications, and the rise of AIoT (AI + IoT) devices.

Learn how building digital twins enhances automotive software development and explore AI's impact on ADAS & connected vehicles through our work with Infineon.

Learn how low-power design techniques such as clock gating, multi voltage domains, and register retention enable efficient IoT SoCs and IoT edge devices.

We discuss the history of technological innovation in the United States and how the balance has shifted west from New Jersey (RCA, Bell Labs) to Silicon Valley.

We're looking back at 2021's breakthroughs & milestones; explore key developments in EDA tools, SoC verification, connected vehicles, and life at Synopsys.

Explore the latest on hyper-convergent chip designs, IC hyperconvergence, and the EDA tools enabling 3DICs and more in the SysMoore era of semiconductor design.

Cryogenic semiconductor IP (cryo-CMOS IP) is critical to scaling quantum computing solutions; learn how it enables co-location of qubits & control electronics.

IC design has come a very long way in a short amount of time. Today, our SoC designs frequently include integrated analog, 100+ Gigabit data rates and 3D stacked DRAM integrated into our SoCs on interposers. In order to keep our heads above water in all of this IC complexity, we need a unified circuit simulation workflow and a fast signoff SPICE and FastSPICE architecture. In this episode of Chalk Talk, Amelia Dalton chats with Hany Elhak from Synopsys about how the unified workflow of the PrimeSim Continuum from Synopsys can help you address systematic and scale complexity for your next IC design.

Once a design goes to tape-out, the real challenges begin. Teams find themselves drowning in data from design-process-test during production ramp-up, and have to cope with data from numerous sources in different formats in the manufacturing test supply chain. In this episode of Chalk Talk, Amelia Dalton chats with Mark Laird of Synopsys in part three of our series on the Silicon LifeCycle Management (SLM) platform, discussing how Yield Explorer and SiliconDash give valuable insight to engineering and manufacturing teams.

In-chip monitoring can significantly alter the lifecycle management landscape. By taking advantage of modern techniques, today’s more complex designs can be optimized even after they are deployed. In this episode of Chalk Talk, Amelia Dalton chats with Stephen Crosher of Synopsys about silicon lifecycle management and how to take full advantage of the optimization opportunities available for scalability, reliability, and much more.

Wouldn’t it be great if we could keep on analyzing our IC designs once they are in the field? After all, simulation and lab measurements can never tell the whole story of how devices will behave in real-world use. In this episode of Chalk Talk, Amelia Dalton chats with Randy Fish of Synopsys about gaining better insight into IC designs through the use of embedded monitors and sensors, and how we can enable a range of new optimizations throughout the lifecycle of our designs.

Physical verification of IC designs at today’s advanced process nodes requires an immense amount of processing power. But, getting your design and verification tools to take full advantage of the compute resources available can be a challenge. In this episode of Chalk Talk, Amelia Dalton chats with Manoz Palaparthi of Synopsys about dramatically improving the performance of your physical verification process. 

Physical verification can take an enormous amount of time, and catching errors early in the process is the best way to avoid costly and time-consuming iterations. In this episode of Chalk Talk, Amelia Dalton chats with Christen Decoin of Synopsys about accelerating physical design productivity with tools and methods that can help catch errors earlier in the design process.

Learn how designers can take advantage of new ways to efficiently pinpoint voltage bottlenecks, drive voltage margin uniformity, and uncover opportunities to fine-tune operating voltages using PrimeShield design robustness solution.

What’s driving the need for a best-in-class solution for library characterization? In the latest Synopsys Designer’s Digest, learn about various SoC design challenges, requirements, and innovative technologies that deliver faster time-to-market with golden signoff quality. Learn how Synopsys’ PrimeLib™ solution addresses the increase in complexity and accuracy needs for advanced nodes and provides designers and foundries accelerated turn-around time and compute resource optimization.

Will your next system require high performance AI? Learn what the latest systems are using for computation, including AI math, floating point and dot product hardware, and processor IP.

This Supercomputing Conference demo shows a seamless interoperability between Synopsys' DesignWare 112G Ethernet PHY IP and Samtec's NovaRay IO and cable assembly. The demo shows excellent performance, BER at 1e-08 and total insertion loss of 37dB. Synopsys and Samtec are enabling the industry with a complete 112G PAM-4 system, which is essential for high-performance computing.

To address increasing variations at advance nodes, design teams add guardband margins and signoff at higher sigma to manage risk, resulting in over-designing, thus paying higher PPA cost. Synopsys’ PrimeShield™ solutions’ innovative ML-driven statistical engine enables full statistical design variation analysis, lowers the overall pessimism, and in some cases catches potential risks of design optimism. In Part 2 of the PrimeShield Techtorial series, Synoposys covers Design Variation Analysis and Variation Robustness, giving a brief overview of each concept and discussing the value each of these brings in improving your power and performance.

Steve Pateras, Senior Director for Hardware Analytics and Test at Synopsys, presents how Silicon Lifecycle Management provides end-to-end analytics data for improved device performance, quality and reduced costs.

This demo features Synopsys’ DesignWare PHY IP for PCIe 6.0, performing at maximum channel loss, with Samtec's connectors in a configurable, GPU-based AI/ML system.

Smart speakers and voice-controlled devices are getting better at understanding requests through NLP. This demo shows how ARC VPX DSP Processor IP moves NLP from the cloud to embedded edge devices for lower latency and excellent power efficiency.

This demo, developed in partnership with Sensor Cortek, executes the FA3D algorithm on ARC EV7x processor with DNN engine. It shows 3D boxes rendered onto objects detected in the video frames, enabling the development of driver assistance systems.

This video features Synopsys' silicon-proven DesignWare 112G Ethernet and PCIe 6.0 PHY IP solutions successfully interoperating with Samtec's AI/ML edge connectors and Amphenol's Direct Attach Copper (DAC) cables with superior Bit Error Rates (BERs) at maximum performance.