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Efabless offers a crowd platform for chip design that uses open source and community models to make the design and commercialization of ICs simple, inexpensive, and accessible to everyone. Product developers use this platform to rapidly, cost-effectively, and reliably create custom silicon. Chip developers use the solution to dramatically reduce cost and time to market for proof of concept of new and exciting ICs.

Efabless just launched the chipIgnite program to provide developers a pre-designed carrier chip including a RISC-V processor and subsystem along with ten square millimeters of silicon for customization. It is a good fit for users who want to create an initial prototype or proof-of-concept for an IP block or full SoC. The starting price is $9,750. For more details, visit


featured contest
Join the AI Generated Open-Source Silicon Design Challenge
Get your AI-generated design manufactured ($9,750 value)! Enter the Efabless open-source silicon design challenge. Use generative AI to create Verilog from natural language prompts, then implement your design using the Efabless chipIgnite platform - including an SoC template (Caravel) providing rapid chip-level integration, and an open-source RTL-to-GDS digital design flow (OpenLane). The winner gets their design manufactured by Efabless. Hurry, though - deadline is June 2!
May 19, 2023
featured paper
Create Your Own Custom Chip for Less than $10K
Imagine what your team could create if you could develop a custom analog/mixed-signal chip for under $10K. Efabless provides a pre-designed carrier chip which includes a RISC-V processor and subsystem along with ten square millimeters of customizable area, bundled together on a wafer shuttle targeting SkyWater's 130nm process and supported by open-source or proprietary tools for just $9,750.
May 24, 2021