Cadence Blog
December 16th
https://youtu.be/izP9iUskcXQ Made at the Cadence Marketing Holiday Party (camera Sean) Monday: RISC-V: Real Products in Volume Tuesday: IEDM: All About Interconnect Wednesday: The Conway...
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December 14th
Yesterday I wrote a sort of overview of the Cadence Automotive Summit that took place in November, in the post Automotive Summit: The Road to an Autonomous Future . Today, the focus in on a key part...
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December 13th
https://youtu.be/SxGTX1reCVw The three highlighted posts for November were: Diwali, the Hindu Festival of Lights...and Photonics, the Silicon Festival of Light Inside Google's TPU Mechanical,...
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December 13th
Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey , approximately half of the...
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Cadence Chalk Talks
A New Advanced IC Packaging Battlefield
Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here for more information about 3D-IC Design Solutions from Cadence Design Systems. |
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the field. In this episode of Chalk Talk, Amelia Dalton chats with Art Schaldenbrand of Cadence Design Systems about designing for reliability with Cadence’s Legato Reliability Solution. Click here for more information about Cadence’s Legato Reliability Solution. |
Scaling Up Vision and AI DSP Performance
For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for Imaging and Neural Networks. |