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Cadence Blog – Latest Posts
BoardSurfers: Training Insights: A Comprehensive Solution for Setting Up PCB Design Parameters
PCB design complexities increase with the increase in the number of parts and layers in a design. For creating these complex designs with maximum efficiency, the design tool should be equipped with...
New Banknote with Alan Turing: "This Is a Foretaste of What Is to Come, and the Shadow of What Is Going to Be"
Today is Alan Turing's birthday. More to the point, today the first £50 banknotes featuring Alan Turing will be issued. I wrote a bit about this when the design was announced in my post...
Pegasus: Get your Wings: Pegasus Run Controls
Have you ever been in a situation where the run has started and you realize that you needed to add two more workers, or drop a couple of them? In such cases, you wait for the run to complete, make...
Overcoming Geometry Model Challenges for CFD Mesh Generation
I have often said that geometry modeling is to mesh generation what turbulence modeling is to CFD: a huge challenge. In the interview below, Cadence's Nick Wyman discusses the scope of this...
New Release - Omnis Version 5.1 Is Out Now!
Want to see it in action? REGISTER FOR WEBINAR T he newest version of the Omnis simulation environment brings a new discrete particle solver, a surface-to-volume mesh module and more than 100 other...
Jim Hogan and Ed McCluskey Named Honorees of the Phil Kaufman Hall of Fame
In February of this year, the ESD Alliance and IEEE CEDA announced the creation of the Phil Kaufman Hall of Fame . On Monday, they announced that the first two honorees are Jim Hogan and Ed...
PIPE SerDes Architecture for PCIe Gen 5 and Beyond
Intel PIPE ( P HY I nterface for P CI E , SATA, USB3.1, DisplayPort and USB4) specification has been ubiquitous PHY interface for accelerating the design and verification of higher layer protocol...
This Week in CFD
It's a short week here at Cadence CFD as we celebrate the Juneteenth holiday today. But CFD doesn't take time off as evidenced by the latest round-up of CFD news. There are several really...
Chalk Talks Featuring Cadence
Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
TensorFlow to RTL with High-Level Synthesis
Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.
Cadence Celsius Thermal Solver
Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.
Mom, I Have a Digital Twin? Now You Tell Me?
Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.
Featured Content from Cadence
Reduce Analog and Mixed-Signal Design Risk with a Unified Design and Simulation Solution
Learn how you can reduce your cost and risk with the Virtuoso and Spectre unified analog and mixed-signal design and simulation solution, offering accuracy, capacity, and high performance.
IP Solutions for a Data-Centric World
High-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, high performance, and small form factor are key requirements for such systems. This paper examines how Cadence’s pre-verified, standards-based design IP can help you deliver on your quality and time-to-market goals.
The Verification World We Know is About to be Revolutionized
Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.
Overcoming Signal Integrity Challenges of 112G Connections on PCB
One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).