Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.
Cadence Blog – Latest Posts
BoardSurfers: How to Create Custom Menus in Allegro SKILL
A menu provides access to frequently used commands or features of an application or program. You can access menu items from the menu bar, typically located at the top of the application window, or a shortcut menu from the right mouse click. There are multiple ways to create c...
Congratulations to Cadence's 2023 Women in Technology Scholarship Recipients
In this edition of our Diversity in Technology Scholarship blog series, we are delighted to congratulate the 12 recipients of Cadence’s 2023 Women in Technology Scholarship by highlighting their achievements and sharing their inspirational academic journeys. In a year of ph...
It’s the Digital Era; Why Not Showcase Your Brand Through a Digital Badge!
In this fast-changing world, every minute, you grab the opportunity to enhance your skills and learning growth. But what’s next? When you gain proficiency and credit for your skills, don’t you want to showcase it to the world? One way is to carry your certificates whereve...
Dr. Shafiya: From a Remote Village to Medical Excellence
In the tranquil village of Bagepalli, just outside Bangalore, Shafiya harbored a dream—to become a doctor and serve her nation. Though a noble dream, it was an expensive one, with her father working as an electrician and her mother a homemaker. A stellar student, Shafiya co...
ONiO Is Creating Battery-Free Solutions
Every year, billions of batteries end up in landfills, resulting in destructive fires, pollution, and toxic waste. The fundamental challenge with today’s electronics is that they all rely on one power source, and that power source is batteries. The solution? Remove the batt...
Back to Basics: Three Use Models for Mixed-Signal Verification
Get back to the basics with Cadence Spectre AMS Designer for Mixed-Signal Verification. Easily incorporate your analog and digital blocks into one simulation Test Bench, script regressions, and run verification from the command line. This could provide a preferred use model t...
Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24
Cadence demonstrated multiple IP for die-to-die connectivity at Chiplet Summit 2024. Conference attendees discussed their chiplet and multi-die design needs with our experts and learned how Cadence’s IP can support them in achieving their system needs with optimum PPA targe...
Training Insights – Struggling with Synthesis to Achieve Best PPA Results?
The ultimate goal of the Cadence Genus Synthesis Solution is very simple: deliver the best possible productivity and Power, Performance, and Area (PPA) during register-transfer-level (RTL) logic synthesis. The real design synthesis journey is not always rosy; there might be s...
Chalk Talks Featuring Cadence
Faster, More Predictable Path to Multi-Chiplet Design Closure
The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.
Enabling Digital Transformation in Electronic Design with Cadence Cloud
With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.
Machine-Learning Optimized Chip Design -- Cadence Design Systems
New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.
Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
Featured Content from Cadence
Faster Path to Multi-Chiplet Design Closure with Better Predictability
Discover how Cadence Integrity 3D-IC is reinventing multi-chiplet design. The Integrity™ 3D-IC Platform provides an industry-first holistic and comprehensive 3D-IC design planning, implementation, and analysis platform to take the full system view and perform system-driven optimization of performance, power, and area (PPA) for chiplets and co-design of interposers, packages, and PCBs for 3D-IC applications
3D-IC Design Challenges and Requirements
While there is great interest in 3D-IC technology, it is still in its early phases. Standard definitions are lacking, the supply chain ecosystem is in flux, and design, analysis, verification, and test challenges need to be resolved. Read this paper to learn about design challenges, ecosystem requirements, and needed solutions. While various types of multi-die packages have been available for many years, this paper focuses on 3D integration and packaging of multiple stacked dies.
Dramatically Improve PPA and Productivity with Generative AI
Discover how you can quickly optimize flows for many blocks concurrently and use that knowledge for your next design. The Cadence Cerebrus Intelligent Chip Explorer is a revolutionary, AI-driven, automated approach to chip design flow optimization. Block engineers specify the design goals, and generative AI features within Cadence Cerebrus Explorer will intelligently optimize the design to meet the power, performance, and area (PPA) goals in a completely automated way.
Industry’s First LLM Technology for Chip Design
Read about the first robust proof of concept of a large language model (LLM) in chip design. To focus on this LLM’s conversation skills would be to misunderstand just how powerful this technology stands to be in solving some of chip design’s most pressing challenges—automating the workflow to reduce errors introduced by humans in creating the design specification, the design itself, and all the project documents needed to create a complex semiconductor device.