Cadence Blog
January 15th
2019 has started --- is this the year of advanced packaging, where system design enablement shifts to the package? If you are attending DesignCon (designcon.com) in Santa Clara, California, in a few...
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January 15th
If you are lucky enough and your company spends a few working days each year on a Hackathon, you must know that it is usually a lot of fun. The latest 2018 Hackathon in Cadence was all about Machine...
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January 15th
As I said in my post about CES last week (see my post Consumer Electronics: 5G, AI, and Air Taxis ), I'm not sure if can read anything into it but the "semiconductor" keynote was given...
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January 14th
Tensilica has been attending CES for many years, before it was acquired by Cadence. The focus used to be on audio processing, with the HiFi family of processors. In fact, as I said in my preview post...
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Cadence Chalk Talks
A New Advanced IC Packaging Battlefield
Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here for more information about 3D-IC Design Solutions from Cadence Design Systems. |
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the field. In this episode of Chalk Talk, Amelia Dalton chats with Art Schaldenbrand of Cadence Design Systems about designing for reliability with Cadence’s Legato Reliability Solution. Click here for more information about Cadence’s Legato Reliability Solution. |
Scaling Up Vision and AI DSP Performance
For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for Imaging and Neural Networks. |