Subscribe Now


Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality.

Cadence Blog – Latest Posts

淺談運算流體力學(CFD)與Pointwise公司
原文出處: Please Excuse the Mesh: CFD and Pointwise 作者: Paul McLellan Cadence於今年四月收購了流體動力學公司Pointwise。在我的前一篇文章探討 Pointwise、PCIe、RISC-V 中有簡短地提到。為了深入瞭解Pointwise,我聯繫了人在德州沃斯堡 (達拉斯人) 的Pointwise執行長 (或稱榮譽執行長)...
May 18, 2021
ASCENT: Analyzing Electrical Stress, Aging, and Faults of PCB Components
Component heating, Joule heating, heat sinks…does the very idea of checking the stress of hundreds of devices on a board for various operating conditions make you reach for a cup of coffee? Is a...
May 18, 2021
How to Verify LPDDR5 from IP to System Level?
LPDDR5 DRAM aims to serve a wide array of markets, including automotive, client PCs and networking systems built for 5G and AI Application. So not only that the JEDEC LPDDR5 specification has...
May 18, 2021
Vietnamese Orphanages and Smartphone Apps
Kids in orphanages have a hard life. You only have to read Oliver Twist to get some idea of that. Or watch the recent hit Netflix drama Queen's Gambit . The best way to secure a future is to get...
May 18, 2021
Virtuoso Meets Maxwell: Making the Ports Ready for Simulations in Clarity 3D Solver
'Virtuoso Meets Maxwell' is a blog series aimed at exploring the capabilities and potential of Virtuoso RF Solution and Virtuoso MultiTech. So, how does Virtuoso meets Maxwell? Now, the...
May 18, 2021
UCLA Leverages High-level Synthesis to Make Rapid Architecture Trade-offs
The Cadence Academic Network values our deep relationships and collaborations with universities. We’re always looking for ways that we can deepen the bond and broaden professor and student knowledge...
May 17, 2021
The Evolution of Computational Aerospace and CFD
In the beginning there was the airfoil. Or more specifically, in 1968 it became clear that something new was needed to help design supercritical airfoils and wings. Today there is serious planning...
May 17, 2021
Extending Quadcopter Drone Flight Time and Range with OMNIS CFD Simulations
Drones have proven to be an efficient solution for a large range of applications within the military, industrial, and private consumer domains. In the past decade, their use has been soaring and...
May 17, 2021

Chalk Talks Featuring Cadence

Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
May 8, 2020
52,080 views
TensorFlow to RTL with High-Level Synthesis
Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.
Apr 17, 2020
48,524 views
Cadence Celsius Thermal Solver
Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.
Apr 13, 2020
40,887 views
Mom, I Have a Digital Twin? Now You Tell Me?
Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.
Apr 10, 2020
47,145 views

Featured Content from Cadence

featured paper
IP Solutions for a Data-Centric World
High-performance computing, data communications, networking, and storage systems are taking center stage in many application areas, driven by newer applications such as analytics, artificial intelligence (AI), genomics, and simulation-intensive workloads. Power efficiency, high performance, and small form factor are key requirements for such systems. This paper examines how Cadence’s pre-verified, standards-based design IP can help you deliver on your quality and time-to-market goals.
May 13, 2021
featured video
The Verification World We Know is About to be Revolutionized
Designs and software are growing in complexity. With verification, you need the right tool at the right time. Cadence® Palladium® Z2 emulation and Protium™ X2 prototyping dynamic duo address challenges of advanced applications from mobile to consumer and hyperscale computing. With a seamlessly integrated flow, unified debug, common interfaces, and testbench content across the systems, the dynamic duo offers rapid design migration and testing from emulation to prototyping. See them in action.
Apr 12, 2021
25,627 views
featured paper
Overcoming Signal Integrity Challenges of 112G Connections on PCB
One big challenge with 112G SerDes is handling signal integrity (SI) issues. By the time the signal winds its way from the transmitter on one chip to packages, across traces on PCBs, through connectors or cables, and arrives at the receiver, the signal is very distorted, making it a challenge to recover the clock and data-bits of the information being transferred. Learn how to handle SI issues and ensure that data is faithfully transmitted with a very low bit error rate (BER).
Click here to download the whitepaper
Jan 4, 2021
featured paper
Speeding Up Large-Scale EM Simulation of ICs Without Compromising Accuracy
With growing on-chip RF content, electromagnetic (EM) simulation of passives is critical — from selecting the right RF design candidates to detecting parasitic coupling. Being on-chip, accurate EM analysis requires a tie in to the process technology with process design kits (PDKs) and foundry-certified EM simulation technology. Anything short of that could compromise the RFIC’s functionality. Learn how to get the highest-in-class accuracy and 10X faster analysis.
Click here to download the whitepaper
Jan 4, 2021