Dear BoardSurfers, I want to unapologetically hijack the normal news and exciting feature information that you are accustomed to reading about in the world of PCB Design blogs to eagerly let you know...

Two big trends that are no surprise, they were big at HOT CHIPS last year and for other events like the Linley Processor Conferences, are every processor is an AI processor, and increasingly most...

CadenceLIVE, Cadence’s annual user conference, has been a great platform for Cadence technology users, developers, and industry experts to connect, share ideas and best practices solve design...

What Is Module Generator? Virtuoso Module Generators, also known as Modgen, is designed to provide a way to generate multiple Pcell instances into a complex, highly matched, structured array. With...

Today, I'm covering two of the biggest chips presented at the recent HOT CHIPS. Ponte Vecchio, Intel's enormous graphics chip intended to be used in Argonne National Laboratories'...

Today is the GF Technology Summit , what used to be called GTC in previous years. GF is, of course, GlobalFoundries. We also announced this morning that the Pegasus Verification System has been...

I came across a question on a social media site about how to know when the absolute maximum ratings for a component have been exceeded? In other words, how do you identify components that are...

今年可說是半導體產業重要的一年，因為電子產品供需失衡、晶片短缺的情況，讓我們更體認到肩負半導體晶片開發的工作，對全世界來說有多麼重要，而如何協助全球經濟向前邁進，也是我們身為半導體產業一份子的使命!...

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.

Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Designing electronics for the data center challenges designers to minimize and dissipate heat. Electrothermal co-simulation requires system components to be accurately modeled and analyzed. Learn about a true 3D solution that offers full system scalability with 3D analysis accuracy for the entire chip, package, board, and enclosure.

Venkat Thanvantri, Cadence VP of Machine Learning R&D, explains how to get better PPA more quickly than you can using a manual iterative approach with the innovative distributing computing technology and reinforcement learning engine of the new Cadence® Cerebrus™ Intelligent Chip Explorer.

To enable continued semiconductor industry growth, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning technology, the next chip design automation revolution is now possible. Learn how engineering teams are able to scale and become more productive using the Cadence® Cerebrus™ Intelligent Chip Explorer, meeting the challenges of increasingly large and more complex SoC designs.

Validate your most sophisticated SoC designs before silicon and stay on schedule. Balance your workload between simulation, emulation and prototyping for complete system validation. You need the right tool for the right job. Emulation meets prototyping -- Cadence Palladium and Protium Dynamic Duo for IP/SoC verification, hardware and software regressions, and early software development.