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Renault Is Lowering Their Carbon Footprint with Cadence
The automotive industry is shifting its focus to reducing CO2 emissions from its vehicles, and it’s no surprise, given the current state of the environment. Renault is a world leader in the automotive market, working on internal combustion engines, hybrid engines, electric vehicles, and hydrogen fuel cells. To lower their carbon footprint, they’re optimizing the efficiency of every part of their system, whether that’s pumps, fans, or rotating parts. And they chose Cadence to help them do so, given our expertise in the CFD field. Cadence Omnis CFD (now Fidelity CFD) helps Renault achieve incredibly accurate results and obtain a high-quality mesh. The optimization tools based on parameterized CAD data, in particular, helped them streamline the design of their water pump. The Minamo tool assisted Renault in extracting and analyzing the influence of different design parameters. Alain Lefebvre, Fluid Systems Simulation Expert at Renault, said, “[Cadence’s] CFD simulation and optimization tools are going to be really a key player at Renault and in the automotive industry right now.” “Designed with Cadence” is a series of videos that showcases creative products and technologies that are accelerating industry innovation using Cadence tools and solutions. Learn more about how Renault is reducing CO2 emissions with Cadence. For more Designed with Cadence videos, check out the Cadence website and YouTube channel .
Breakfast Bytes Guide to Berlin
I was in Munich for CadenceLIVE Europe and took that opportunity to write Breakfast Bytes Guide to Munich . The next day, my wife and I took the train to Berlin. Somehow, I'd never been to Berlin before. There is clearly a lot of history here. Getting To and Around Berlin Obviously, you can fly into Berlin. But if you are coming here from somewhere else in Germany, it is probably easiest to take the train. Download the DB Navigator App and you can book tickets, explore the availability of trains, and reserve seats, all without needing to go near a train station (well, until you depart, obviously). Your ticket, a barcode, will get scanned on the train by the train conductor. You can book for more than one person on the same ticket. Then, once you get to Berlin, there is an app for the subway (U-Bahn and S-Bahn) called BVG, which lets you book trips (or an all-day ticket and other options). You end up with a barcode on your phone that you will need to show to the ticket inspector in the unlikely event you get inspected. Otherwise, you don't need to do anything with the ticket. Each person needs their own ticket on their own phone. History of Berlin Just the very recent history. In 1871, Berlin became the capital of a newly unified Germany. Then the Second World War happened, and in the aftermath, Berlin ended up as an island of West Germany surrounded by East Germany, and with a hundred-mile wall encircling the city. The capital of West Germany was moved to Bonn. In 1989, the wall came down, and in 1990 East and West Germany were reunified to give us the situation today with just Germany, or technically the Federal Republic of Germany. Berlin became the capital again. This turned out to be good for Munich, too. Siemens had been headquartered in Berlin, but when Berlin was relatively isolated it moved its headquarters to Munich, at the time considered a sleepy backward agricultural town (although BMW and more were already there). But that decision made Munich the electronic capital of Germany and a very wealthy city in the nation. After reunification, the most popular place to build semiconductor manufacturing fabs was Dresden (in former East Germany). AMD built "fab 1" there (now GlobalFoundries), Qimonda (the memory spinout from Siemens that failed) had a fab. Bosch has built a fab there. XFAB is there. And more. However, Intel plans its new fabs in Magdeburg, also in former East Germany but further North. Famous Sights Everyone will have their own list of what they want to see. One challenge, both to get a clear view and to take good photos, is that everywhere in Berlin seems to be a construction site. Anyway, here are some obvious choices of what to see: The Brandenburg Gate . This is an iconic symbol not just for Germany, but for Europe. I can't think of any similar triumphant structure in Brussels (and Mannekin Pis is hardly going to fill the gap!). The Reichstag . You can visit the Reichstag for free, but you must book at least three days in advance and get a timeslot. I couldn't get a slot, so I can't tell you what you will see inside, except I know you get to go inside the Norman Foster glass dome on the top (see my photo). Memorial to the Murdered Jews of Europe . There is also a free museum underneath with more details, photos, and more. The Berlin Wall Memorial . This a preserved section of the Berlin Wall that separated Berlin from East Germany until 1989. Museums Like Munich, Berlin has literally dozens of museums. Here are a couple I visited. Munich has the Deutschesmuseum . Berlin has Deutsches Technikmuseum or German Technical Museum in English. I will cover this in a separate post. Arguably, it contains the first programmable computer, dating to the mid-1930s. There is a fashion for repurposing obsolete buildings to be art galleries. The most famous must be the Musée d'Orsay in Paris (a repurposed train station, the Gare d'Orsay) or perhaps Tate Modern in London (a repurposed power station). Berlin has one, too, the Hamburger Banhof , which sounds like something off a McDonald's menu but is, in fact, a repurposed train station, too, the old station for the Berlin-Hamburg line. There was nothing in the main hall when we were there. The art wasn't great that day either, so like some other galleries (the Tate in St Ives, Cornwall, for example), the building was the most interesting thing there. Tiergarten Munich has the Englishergarten in the heart of the city. Berlin has the Tiergarten , stretching a long way from the Brandenburg Gate away from the center of the city. It is a semi-wild forest in the center of the city. It is no longer the largest park in the city since the old Tempelhof Airport, which closed in 2008, is now a park. Currywurst In Munich, I said you had to try weisswurst, the most iconic Bavarian sausage. Well, in Berlin, you have to try currywurst . Not only is this the most iconic Berlin sausage, it is the most iconic Berlin dish. Sometimes it is served whole with fries, as in the photo I took of my Thanksgiving lunch. Sometimes the sausages are cut up into chunks and served in the curry sauce. Sign up for Sunday Brunch, the weekly Breakfast Bytes email. .
Training Insights - Dude, Where's My Software?
You will notice a big change when you try to download the latest version of Innovus, Genus, or Joules on our Cadence download site, downloads.cadence.com . Instead of the expected INNOVUS221 or GENUS221, or JOULES221 releases, you will find DDI221, which includes the 22.1 versions of all three tools. You might ask why? According to Rod Metcalfe , our Product Management Group Director, ”The integrated Cadence digital full flow has always shared core engines across the whole flow, so Genus uses Innovus technology and vice versa. Combining all the Digital Design and Implementation (DDI) tools into one DDI 22.1 release makes it much easier for our customers to install everything in one simple download.” We have also just released the Innovus and Genus 22.1 online courses. Our online courses are included with Cadence Support. Here are the Innovus and Genus 22.1 course links to register: Genus Synthesis Solution with Stylus Common UI Innovus Block Implementation with Stylus Common UI Stay tuned for the Joules 22.1 course release. Each of our courses includes a badge exam to test your proficiency with the materials. When you pass the exam, you will receive a badge from Credly to proudly display on social media. Training Bytes (Videos) http://support.cadence.com/TrainingBytes/Genus http://support.cadence.com/TrainingBytes/Innovus For more information on Cadence digital design and signoff products and services, visit www.cadence.com . If you don´t have an account on the Cadence Learning and Support portal yet, please find further information on how to get one here. To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails. So, now that you know how your software is bundled, happy learning! Vinita
Knowledge Booster Training Bytes - Enhance Layout Productivity with Virtuoso CLE
Are you using the sequential Virtuoso Layout flow? Have you ever wished to perform multiple layout designing and editing tasks in parallel so that more work can be done in given time? If your answer is yes, Virtuoso Concurrent Layout (CLE with E for editing ) might be the solution for you. Use it to create multiple partitions in the design and have designers work in parallel, which helps save time and enhances your layout productivity! In this Knowledge Booster blog, let’s talk about and explore how to do layout design tasks using concurrent editing. The blog: Introduces the training materials and videos that can help you understand and use this feature Shows how to earn a digital badge by passing an exam for the course What Is Concurrent Layout Editing? Virtuoso Concurrent Layout Editor is a layout editing environment that enables designers to work concurrently on the same cellview within the Virtuoso environment. As the designers work in parallel, using concurrent layout helps in bringing down the designing time and, as a result, increases productivity. You can perform concurrent editing in Virtuoso Layout Suite XL combined with 4 GXL flexible license tokens and Virtuoso Layout Suite EXL. Concurrent Layout Flow 1. Initialize the Top Design for Concurrent Layout Editing: The first task for the manager is to initialize the design to get it ready for concurrent editing. 2. Define the Design Partitions: After the design is initialized, you can start defining the area-based/layer-based design partitions based on your editing requirements. 3. Edit the Design Partitions: After the required design partitions and design partition views are created, designers can start editing the allocated design partition views. 4. Import the Peer Design Partitions: You can import the changes made in the peer design partitions and view the updated design. 5. Merge the Top Design: After the designers have completed editing the design and submitted their respective design partitions for merge, the manager needs to review these requests and then either approve or reject the merge requests. The manager needs to commit the changes in CLE to complete the merge process and save the merged changes into the top design. After all the design partitions are merged with the top design, the manager can delete and clear all the design partitions and exit the Concurrent Layout Editing environment. What’s Next? Take the free Virtuoso Layout Pro: T8 Virtuoso Concurrent Layout Editing online course On the Cadence Learning and Support portal (login required) you can view the Virtuoso Concurrent Layout Editing Training Byte Channel Videos: Setting Up the Concurrent Layout Editing Environment Initializing and Partitioning the Top Design in Manager Mode Editing the Design Partition userA in Designer Mode Editing the Design Partition userB in Designer Mode Merging/Committing the Top Design in Manager Mode Quiz on Virtuoso Concurrent Layout Editing And earn a Digital Badge by passing an exam for the course. Information and FAQs To find information on how to get an account on the Cadence Learning and Support portal, see the Support page. To stay up-to-date with the latest news and information about Cadence training and webinars, subscribe to the Cadence Training emails. If you have questions about courses, schedules, online, public, or live onsite training, reach out to us at Cadence Training . Related Resources Online Courses Virtuoso Layout Pro: T1 Environment and Basic Commands (L) Virtuoso Layout Pro: T2 Create and Edit Commands (L) Virtuoso Layout Pro: T3 Basic Commands (XL) Virtuoso Layout Pro: T4 Advanced Commands (XL) Virtuoso Layout Pro: T5 Interactive Routing (XL) Virtuoso Layout Pro: T6 Constraint-Driven Flow and Power Routing Virtuoso Layout Pro: T7 Module Generator and Floorplanner (XL/GXL) Virtuoso Layout Pro: T9 Virtuoso Design Planner Blogs Virtuosity: Synergize with CLE - Work Concurrently Across Geographies Virtuosity: Concurrently Editing a Hierarchical Cellview Virtuoso: The Next Overture – Concurrent Layout – a New Methodology for Team Design Rapid Adoption Kit Virtuoso Concurrent Layout Editing User Guide Virtuoso Concurrent Layout User Guide Contact Us For any questions, general feedback, or even if you want to suggest a future blog topic, write to firstname.lastname@example.org . About Knowledge Booster Training Bytes Knowledge Booster Training Bytes is an online journal that relays information about Cadence Training videos, online courses, and upcoming webinars that are available in the Learning section of the Cadence Learning and Support portal. This blog category brings you direct links to these videos, courses, and other related material, on a regular basis. Subscribe to receive email notifications about our latest Custom IC Design blog posts. Baby Ravi On behalf of the Cadence Training team
Software-Defined Vehicles: The Automotive Revolution with Silicon at its Heart
The automotive sector is undergoing immense change. The retirement of the internal combustion engine (ICE) in favor of electrified powertrains and a shift towards autonomy has provided carmakers the opportunity to reimagine and redefine the entire automotive experience: how a car looks, works, and behaves, from the tires up. But such change isn’t easy. An industry founded on the manufacture of heavy steel boxes powered by rumbling, fossil-fueled engines and manually controlled via a dashboard of hard-wired levers, switches and dials has found itself outpaced, outmoded and out of tune with the expectations and realities of today. A new generation of car buyers, prioritizing personalization and connectivity over horsepower or external styling, has seen the in-car experience become the battleground in automotive differentiation. Consumers have seen the prices at the fuel pumps.They’ve seen how easily connected, upgraded, and personalized their smart devices are over the air (OTA), and they’re wondering why they still need to take their car to a dealership to fix a software bug. They want something smarter, safer, cheaper, more sustainable to run and more rewarding to own. So while powertrain electrification and autonomy remain big news (and is likely to be until the last manually driveable, fossil-fueled vehicle rolls of production lines), there’s an even bigger story unfolding behind the scenes – the move to the software-defined vehicle. Software-Defined Vehicles (SDVs) Consider the benefits of aggregating all the disparate, hard-coded electromechanical systems of a car into a single, interconnected backbone of technology in which every parameter, every application and every mechanism is controlled by lines of code rather than physical mechanics and can therefore be upgraded, fixed, and personalized – potentially over the air. This is the promise of the software-defined vehicle (SDV). Consumers get the promise of a better in-car experience as mileage increases. Dealers get new revenue opportunities and ways to build brand loyalty and customer relationships over time through new features and enhancements. And carmakers, OEMs and tier one suppliers get the opportunity to fix issues instantly, avoid expensive recalls and battle to deliver a safer, more efficient, and more enjoyable experience than their competitors. A software-defined vehicle is a future-proof vehicle. Imagine stepping into your car and being informed that its brakes are now 5 percent more efficient or that its battery will now last 5 percent longer. We’re used to this with our smartphones – now it’s time to expect it of our vehicles. Automotive Intelligence An SDV in which every function is controlled by software is also capable of operating autonomously – so long as the physical sensors required for it to understand its surroundings and environmental conditions are present. Today, most autonomous capability centers around advanced driver assistance systems (ADAS), such as lane assistance on the highway or adaptive cruise control. This is enabled by a range of sensors, from cameras to mmWave radar, lidar, gyroscopes, and GPS. All of these sensors generate large amounts of data – and even if a vehicle isn’t actively driving itself, this data is a goldmine in training AI models to drive autonomously – learning from how they are driven in each scenario to devise the optimum output from any given situation and the implications of each decision. Powerful Performance at the Edge But herein lies a larger problem. Forecasts have suggested that while modern vehicles generate around 25 gigabytes of data every hour, fully autonomous vehicles will exceed this by more than 100 times. That’s not just a lot of data—that’s a tsunami. Not only would this push global networks to their limit, it would also mandate global cloud data centers to work harder than ever before, increasing their energy expenditure and carbon footprint exponentially. Instead, vehicles need to be able to make sense of this data themselves, using what we call sensor fusion to combine data sets in real-time and spot patterns. This is fundamentally important for autonomous driving, but it’s also important for things like predictive maintenance, where the car identifies degradation or variation of some kind and can adjust parameters to avoid damage or mitigate potential safety issues. That’s why the software-defined vehicle needs hardware capable of handling everything from simple safety check up to complex AI processing within the vehicle. A Complex Ecosystem The compute platform within SDVs is complex, given the number of sensors and actuators required throughout the vehicle. A powerful central computer acts as the ‘brain’ of the vehicle, delivering autonomous driving and general vehicle functions. This central computer is connected to multiple zonal controllers, which serve as hubs for specific groups of functions. One single zonal controller might support the car’s headlights, folding and heated mirrors, door locks, windows, seat controls, and so on, while another might be focused on powertrain management and ensuring optimal load on the vehicle’s battery. One step down from the zonal controllers, we have potentially hundreds of microcontrollers (MCUs) integrated into electronic control units (ECUs) throughout the vehicle, each supporting single-function operations (one inside the headlights, one controlling the door locks, and so on). There’s also a major role for fast, accurate real-time microcontrollers. Real-time processors are designed to always meet timing constraints, and are generally reserved for mission-critical tasks such as automotive and industrial applications. Because we can rely on them to perform their functions in a given timeframe, they’re ideal for safety and autonomous applications, whereas a general-purpose processor might encounter a delay, leading to a potentially catastrophic outcome. Semiconductor Electronics All in all, that is an incredible amount of silicon under the hood. The vision of the software-defined vehicle will live or die on how well this vastly complex network of hardware is integrated into each vehicle. Today, ongoing disruptions in the electronics supply chain are exacerbated by higher-than-expected demand with less-elastic manufacturing capacity and longer lead times. Some Tier-1 subsystem suppliers are bringing semiconductor design in-house to further control supply and inventory and to optimize the overall system. To ensure success, they are hiring semiconductor experts but are competing in a limited talent pool, amplifying the need for automated semiconductor design tools. Automotive chips have been fabricated using older semiconductor manufacturing processes to save costs. The revolution in automotive electronics, however, is driven by high-value features, which require implementation in the most advanced semiconductor manufacturing processes and the latest process nodes due to the needed performance, design size, and power consumption. Using AI to overcome this escalating design complexity is showing great promise in both productivity and optimization. A New Automotive Design Paradigm The automobile has changed forever. Electrification and AI have enabled improvements in efficiency, performance, and safety. While some drivers may think only about how quickly they will arrive at a destination, increasingly, there's more focus on what happens along the journey — the in-car experience. Intelligent vehicles are enabled by semiconductors, data, and decision-making AI, causing automotive system complexity to grow exponentially and requiring more sophisticated design and test technologies. To achieve the necessary performance as well as sustainable design goals and safe operations, these elements can no longer be designed in isolation. A new design collaboration paradigm must be embraced where engineers from different disciplines unite to achieve their common goal.
Advanced Auto-Routing for TSMC InFO Technologies
At the recent TSMC OIP Symposium, John Park presented Advanced Auto-Routing for TSMC InFO Technologies . InFO stands for "integrated fanout" and is the lower performance, lower complexity technology for advanced packaging. For details of TSMC's whole packaging portfolio, see my post TSMC OIP: 3DFabric Alliance and 3Dblox . Here's the slide TSMC presented from that presentation on InFO. As you can see, InFO comes in a number of different flavors. The first implementation, back in 2016, was InFO-PoP for mobile, adding a DRAM package on top of the application processor die. Then InFO_oS for HPC, allowing multiple die to be put in increasingly large packages. The latest technology, InFO_3D allows logic to be stacked vertically on logic, with routing underneath to distribute the power delivery network and signals. I won't reiterate all the arguments in favor of using advanced packaging rather than simply scaling and putting everything in the most advanced node. We'll just take that as a given in this post. For John's longer exposition on this topic, see my post EDPS: When Chips Become 3D Systems and the Challenges of 3DHI . As I've said before, advanced packaging and heterogeneous integration have become the hottest area in all of semiconductor design today. Routing Has Become the Primary Bottleneck The table above shows how much more challenging routing has become. On the left are the requirements for flip-chip ball-grid-array (FCBGA). There are, at most, a few thousand connections. There is RDL signal routing to spread out the signals to the solder balls from the comparatively small single die. On the right is the technology we are talking about today, 3D heterogeneous integration wafer-level packaging, or 3DHI-WLP. The package typically contains multiple chiplets, perhaps tens of thousands of signal connections, so the RDL signal routing is not just distributing the signals but also handling the chiplet-to-chiplet routing too. Power routing is another complication with a number of feasible approaches. Diving down to another level of detail, among the challenges are: Chiplet-to-chiplet and fanout RDL routing requirements Efficient pin-escape patterns Routing channel density Complex via stacking Interconnect fillets for yield improvement Routing signals and power nets together for optimal density Reuse support for repeatable patterns Power/ground via placement To address these challenges, Cadence and TSMC have been working together to develop next-generation automatic signal routing solutions for InFO technologies: Multi-threaded automated routing engine for high-capacity design support Routing that supports TSMC's electrical, physical, and yield rules Support for shielding, differential signals, and fillet/teardrop insertion (see on right) Pre-seed escape routing with reuse structures Slice-based routing to support replication The automatic power routing solution: Mix and match IC-style and BGA-style power routing (stripes/rails and planes) Locking structures to prevent changes when working on neighboring areas Savable configurations for use in subsequent designs Automatically define shape boundary styles (puzzle pieces) based on power-pin groupings Putting it all together, the flow is: Topology routing Escape routing Power routing Detailed routing Pattern replication Fillet insertion Final DRC Results As you can see from the above tables, the speedups are impressive (factors of over 100). And using multi-threaded detailed routing with lots of cores also results in speedups of over 10X. Summary The primary bottleneck for laying out today's advanced packages is routing This applies both to signal routing (RDL/D2D) and power routing A next-generation solution is required to reduce the bottleneck and support large designs Cadence and TSMC have partnered to develop next-gen signal and power auto-routers for InFO packaging technologies Natively massively parallelized Combines multiple routing techniques Portable multi-layer routing engine, Cadence's Allegro ICP Support of replication Support of TSMC routing constraints and DRC rules Sign up for Sunday Brunch, the weekly Breakfast Bytes email. .
Virtuoso ICADVM20.1 ISR29 and IC6.1.8 ISR29 Now Available
The ICADVM20.1 ISR29 and IC6.1.8 ISR29 production releases are now available for download at Cadence Downloads . For information on supported platforms and other release compatibility information, see the README.txt file in the installation hierarchy. ICADVM20.1 ISR29 IC6.1.8 ISR29 Here's a list of the highlights from our recent ICADVM20.1 and IC6.1.8 releases: Selection of Die Bumps or BGA Balls in the Palette Assistant (Virtuoso RF Solution) Use Pins in the Objects panel of the Palette assistant to select die bumps and BGA balls. Assisted Synchronization of Virtuoso and SiP Layouts (Virtuoso RF Solution) Use the newly-introduced assisted flows to update changes made to a Virtuoso RF Solution compatible layout to the corresponding SiP file and vice versa. Support for Fillet Creation (Virtuoso RF Solution) Use the Fillet tab of the Metal Density Options form to create and control fillet insertion in the design. Fillets are an extra etch added to prevent acid traps on a design, which in turn improves yield and manufacturability. Using the DSPF-in-the-Middle Flow for AMS Simulations (Virtuoso ADE Explorer, Virtuoso ADE Assembler) Use the check box Using HED Config for DSPF Blackbox in the Simulation Files Setup form for AMS simulator to enable the DSPF-in-the-middle flow for ADE Explorer or ADE Assembler. Sweep DSPF Files Using the VAR Function (Virtuoso ADE Explorer, Virtuoso ADE Assembler) Use the VAR function to sweep DSPF files specified in the Simulation Files Setup form or in the Corners Setup form. For more details on these and all the other new and enhanced features introduced in this release, see: What’s New in Virtuoso IC6.1.8 ISR29 and ICADVM20.1 ISR29 (Application Notes) Virtuoso IC6.1.8, ICADVM18.1 & ICADVM20.1 ISR: What's New Library ICADVM20.1 What's New IC6.1.8 What's New Please send questions and feedback to email@example.com . Virtuoso Release Team
Tulasi Narayanaswamy: Against All Odds
Tulasi's Story Tulasi is a brilliant young woman who has the aspiration, grit, and determination to be successful. Coming from a low-income family living in a remote village in Karnataka, Tulasi had limited opportunities and access to higher education. Tulasi's parents work as caretakers in a farmhouse and live with their three daughters in a small semi-constructed room provided by their employer. Their only supplementary income comes from raising sheep. Tulasi travelled seven kilometers daily to school, where she completed her 12 th -grade education. She wanted to pursue a course in engineering but was conscious that her parents would not be able to afford the fees. When Tulasi learned about the Cadence Scholarship Program through her school, she was determined to apply. For her, this was a golden opportunity—perhaps her only opportunity—for higher education. She prepared for the interview through long hours of studying and impressed the panelists during the scholarship screening round with her dedication and perseverance, despite her hardships and limited resources. With Cadence Scholarship Program support, Tulasi enrolled in a well-reputed engineering college, BNM Institute of Technology, Bangalore, to pursue a Bachelor of Engineering degree in Information Science and Engineering. Throughout the Cadence Scholarship Program, her Cadence mentor, Ritwika Mondal, supported her by helping her improve her written and verbal communication skills and giving her invaluable career advice. Tulasi graduated in 2022 with high marks and received a job offer from a well-known company with a salary that is at par with the best in the industry. She is extremely motivated to succeed in life, whether it’s through her studies or her new job. Her goal of supporting her parents and sisters has now been realized. It's heart-warming to see how a little help in someone's life can go such a long way. Tulasi has inspired her younger sisters to pursue their education despite challenges. Tulasi says, "I am proud of myself and my mentor who made my success story a reality “Receiving the scholarship has paved the way to better myself, have a career I am proud of, help people in need, and support my family. Every act of kindness is like a ripple in a pond," she concluded. Cadence Scholarship Program Introduced six years ago in India, the Cadence Scholarship Program aims at addressing the issue of retaining students from underprivileged backgrounds in the academic cycle through funding and support to undertake graduation and professional courses for livelihood. Over the years, it has benefited more than 400 students across Delhi/NCR, Bangalore, Pune, and Ahmedabad. The execution and administration of the program is managed by our NGO partners Concern India Foundation (CIF) and Joining Hands. The students are selected through a rigorous process of due diligence carried out by Joining Hands. Concern India Foundation oversees the student’s performance throughout their coursework. Cadence employees in each of these locations volunteer as mentors to help them with their studies, develop their personalities and improve their communication and employability skills.
Chalk Talks Featuring Cadence
Faster, More Predictable Path to Multi-Chiplet Design Closure
The challenges for 3D IC design are greater than standard chip design - but they are not insurmountable. In this episode of Chalk Talk, Amelia Dalton chats with Vinay Patwardhan from Cadence Design Systems about the variety of challenges faced by 3D IC designers today and how Cadence’s integrated, high-capacity Integrity 3D IC Platform, with its 3D design planning and implementation cockpit, flow manager and co-design capabilities will not only help you with your next 3D IC design.
Enabling Digital Transformation in Electronic Design with Cadence Cloud
With increasing design sizes, complexity of advanced nodes, and faster time to market requirements - design teams are looking for scalability, simplicity, flexibility and agility. In today’s Chalk Talk, Amelia Dalton chats with Mahesh Turaga about the details of Cadence’s end to end cloud portfolio, how you can extend your on-prem environment with the push of a button with Cadence’s new hybrid cloud and Cadence’s Cloud solutions you can help you from design creation to systems design and more.
Machine-Learning Optimized Chip Design -- Cadence Design Systems
New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.
Cloud Computing for Electronic Design (Are We There Yet?)
When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.
Featured Content from Cadence
How to Harness the Massive Amounts of Design Data Generated with Every Project
Long gone are the days where engineers imported text-based reports into spreadsheets and sorted the columns to extract useful information. Introducing the Cadence Joint Enterprise Data and AI (JedAI) platform created from the ground up for EDA data such as waveforms, workflows, RTL netlists, and more. Using Cadence JedAI, engineering teams can visualize the data and trends and implement practical design strategies across the entire SoC design for improved productivity and quality of results.
Get Ready to Accelerate Productivity and Time to Market with Overnight Chip-Level Signoff Closure
Is design closure taking too long? Introducing the Cadence Certus Closure Solution, a revolutionary new tool that optimizes and delivers overnight design closure for both the chip and subsystem. Learn how the solution supports the largest chip design projects with unlimited capacity while substantially improving productivity by up to 10X.
Butterfly Network Puts 3D Ultrasound on a Chip with Cadence
About two-thirds of the world’s population lacks access to medical imaging, whether in developing nations or in first-world countries with underserved communities. Driven by a vision of improving the standard of healthcare around the world, Butterfly Network designs and makes the first 3D Ultrasound imaging system and whole-body imager that's small enough to be carried in your pocket.
Leverage Big Data and AI to Optimize Verification and Productivity Across an Entire SoC
Optimize your verification workload, boost coverage, and accelerate root cause analysis to reduce silicon bugs and accelerate your time to market with Cadence Verisium AI-Driven Verification. Learn how this generational shift from single-run, single-engine algorithms to algorithms leverages big data and AI across multiple runs of multiple engines throughout an entire SoC verification campaign.