We will not let today's gray and wet weather in Fort Worth (home of Cadence's Pointwise team) put a damper on the week's CFD news which contains something from the highbrow to the...

Cadence has quite a long history of releasing Generic PDKs for demonstration purposes. All Rapid Adoption Kits (RAKs) are based on one of the GPDKs, which are downloadable from support.cadence.com ....

In this Knowledge Booster Training Bytes blog, let's talk about the Virtuoso Schematic Editor tool that provides numerous capabilities to facilitate fast and easy design entry. This includes...

Design and Test Europe, normally known as just DATE, is back to its usual March schedule for 2022. It will take place from 14th to 23rd March. The plans are for this to be a hybrid event, with the...

We all want to be sure, or as sure as we can be, that our products will work as expected in the real world under circumstances that may not always be under our control or per our specifications. We...

I used to have this calculator, and I have a feeling it is actually somewhere in my office at Cadence, but since I've not been there for over 18 months I can't really check. This is the Braun...

Have you used AXL-SKILL to create custom menus for frequently-used design tasks? That saves you a lot of time and frees you from remembering command names or from typing them every time. An even...

Coming up on 20th October is this year's CadenceConnect Mission Critical event. It will be a digital event. Note that all times given in this blog post are Eastern , not Pacific like many Cadence...

New applications and technology are driving demand for even more compute and functionality in the devices we use every day. System on chip (SoC) designs are quickly migrating to new process nodes, and rapidly growing in size and complexity. In this episode of Chalk Talk, Amelia Dalton chats with Rod Metcalfe about how machine learning combined with distributed computing offers new capabilities to automate and scale RTL to GDS chip implementation flows, enabling design teams to support more, and increasingly complex, SoC projects.

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.

Designing electronics for the data center challenges designers to minimize and dissipate heat. Electrothermal co-simulation requires system components to be accurately modeled and analyzed. Learn about a true 3D solution that offers full system scalability with 3D analysis accuracy for the entire chip, package, board, and enclosure.

Venkat Thanvantri, Cadence VP of Machine Learning R&D, explains how to get better PPA more quickly than you can using a manual iterative approach with the innovative distributing computing technology and reinforcement learning engine of the new Cadence® Cerebrus™ Intelligent Chip Explorer.

To enable continued semiconductor industry growth, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning technology, the next chip design automation revolution is now possible. Learn how engineering teams are able to scale and become more productive using the Cadence® Cerebrus™ Intelligent Chip Explorer, meeting the challenges of increasingly large and more complex SoC designs.

Validate your most sophisticated SoC designs before silicon and stay on schedule. Balance your workload between simulation, emulation and prototyping for complete system validation. You need the right tool for the right job. Emulation meets prototyping -- Cadence Palladium and Protium Dynamic Duo for IP/SoC verification, hardware and software regressions, and early software development.