The Team RF "μWaveRiders" blog series is a showcase for Cadence AWR RF products. Monthly topics will vary between Cadence AWR Design Environment release highlights, feature videos, Cadence...

CadenceLIVE Europe is on October 19 and will be a digital event. Let me give you a preview of what is coming up and some reasons to attend. As usual, there are keynotes, technical updates,...

“μWaveRiders” 是一系列旨在探讨 Cadence AWR RF 产品的博客，按月更新，其内容涵盖 Cadence AWR Design Environment 最新的核心功能，专题视频，Cadence Academic Network 或者之前 AWR University Program 的相关新闻，以及产品提示、技巧和核心功能介绍 AWR Design Environment...

This morning Cadence announced the release of the Helium Virtual and Hybrid Studio. This is a next-generation engine for hardware/software co-verification and debug. The full virtual model provides...

The concept of Trusted Execution Environments (TEE) was developed in the early 2000s to standardize key encryptions, end-to-end security and authenticity, and confidentiality of devices in a system....

The Basics of CFD in 8 Weeks - Free Online Course Learn the basics of CFD in eight classes across eight weeks and gain hands-on experience using commercial, flow-simulation software! Lasting approx....

Placing component leads accurately as per the datasheet is an important task while creating a package footprint symbol. As the pin pitch goes down, the size and location of the component lead play a...

As a chip designer, you’re probably spending as much headspace on security threats as you are on traditional challenges like power, speed, and functionality . Recent microarchitectural...

When your project is at crunch time, a shortage of server capacity can bring your schedule to a crawl. But, the rest of the year, having a bunch of extra servers sitting around idle can be extremely expensive. Cloud-based EDA lets you have exactly the compute resources you need, when you need them. In this episode of Chalk Talk, Amelia Dalton chats with Craig Johnson of Cadence Design Systems about Cadence’s cloud-based EDA solutions.

Bridging the gap from the AI and data science world to the RTL and hardware design world can be challenging. High-level synthesis (HLS) can provide a mechanism to get from AI frameworks like TensorFlow into synthesizable RTL, enabling the development of high-performance inference architectures. In this episode of Chalk Talk, Amelia Dalton chats with Dave Apte of Cadence Design Systems about doing AI design with HLS.

Electrical-thermal co-simulation can dramatically improve the system design process, allowing thermal design adaptation to be done much earlier. The Cadence Celsius Thermal Solver is a complete electrical-thermal co-simulation solution for the full hierarchy of electronic systems from ICs to physical enclosures. In this episode of Chalk Talk, Amelia Dalton chats with CT Kao of Cadence Design Systems about how the Celsius Thermal Solver can help detect and mitigate thermal issues early in the design process.

Today, one engineer’s “system” is another engineer’s “component.” The complexity of system-level design has skyrocketed with the new wave of intelligent systems. In this world, optimizing electronic system designs requires digital twins, shifting left, virtual platforms, and emulation to sort everything out. In this episode of Chalk Talk, Amelia Dalton chats with Frank Schirrmeister of Cadence Design Systems about system-level optimization.

Designing electronics for the data center challenges designers to minimize and dissipate heat. Electrothermal co-simulation requires system components to be accurately modeled and analyzed. Learn about a true 3D solution that offers full system scalability with 3D analysis accuracy for the entire chip, package, board, and enclosure.

Venkat Thanvantri, Cadence VP of Machine Learning R&D, explains how to get better PPA more quickly than you can using a manual iterative approach with the innovative distributing computing technology and reinforcement learning engine of the new Cadence® Cerebrus™ Intelligent Chip Explorer.

To enable continued semiconductor industry growth, the chip design process must become more efficient. With the availability of massive, cloud-enabled, distributed computing and advancements in machine learning technology, the next chip design automation revolution is now possible. Learn how engineering teams are able to scale and become more productive using the Cadence® Cerebrus™ Intelligent Chip Explorer, meeting the challenges of increasingly large and more complex SoC designs.

Validate your most sophisticated SoC designs before silicon and stay on schedule. Balance your workload between simulation, emulation and prototyping for complete system validation. You need the right tool for the right job. Emulation meets prototyping -- Cadence Palladium and Protium Dynamic Duo for IP/SoC verification, hardware and software regressions, and early software development.