Cadence Blog
January 18th
It's Martin Luther King day on Monday, and Cadence is off. I think that this is the first time I have ever got it as a holiday, rather than moving it to somewhere like July 3rd. Breakfast Bytes...
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January 17th
Happy new year! We want to invite you to visit us in booth 711 on the DesignCon Expo floor. Learn about how we can address your design challenges with Cadence ® Sigrity signal integrity and...
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January 17th
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso® ADE Assembler , I am writing this third blog in the series to share...
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January 17th
At IEDM in December, the Sunday preceding the conference proper consists of two short courses, traditionally one logic-related and one memory-related. I always attend the logic one, since that is the...
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Cadence Chalk Talks
A New Advanced IC Packaging Battlefield
Today, advanced packaging technology has created a new battleground where 2.5D packaging and heterogeneous design drive constraints that span semiconductor, packaging, board, and even system-level design. In this episode of Chalk Talk, Amelia Dalton chats with John Park of Cadence Design Systems about new techniques and tools for advanced IC packaging design. Click here for more information about 3D-IC Design Solutions from Cadence Design Systems. |
Designing High-Reliability Analog and Mixed-Signal ICs for Mission-Critical Applications
Designing products for reliability and longevity requires a different mindset – and a different tool set from the more common “just get it out the door” engineering methodology. We need to focus on all phases of product life, and do a diligent analysis of the mechanisms that can lead to premature failure in the field. In this episode of Chalk Talk, Amelia Dalton chats with Art Schaldenbrand of Cadence Design Systems about designing for reliability with Cadence’s Legato Reliability Solution. Click here for more information about Cadence’s Legato Reliability Solution. |
Scaling Up Vision and AI DSP Performance
For high-performance, low-power processing of AI and machine vision algorithms, latency can be critical. In this episode of Chalk Talk, Amelia Dalton chats with Pulin Desai from Cadence Design Systems about the using the new Vision Q6 processor core for embedded vision and AI applications. Click here for more information about Vision DSPs for Imaging and Neural Networks. |