IRVINE, Calif., January 27, 2025– DesignCon 2025 – TeraSignal, a leader in intelligent interconnect technology, announced the successful interoperability demonstration between its TSLink intelligent chip-to-module (C2M) interconnect and Synopsys’ 112G Ethernet PHY IP at DesignCon 2025. This demonstration showcases TeraSignal’s and Synopsys’ joint commitment to developing low-power and low-latency technologies for high-performance AI and data center infrastructure. TSLink delivers optimized link settings, real-time performance monitoring, and a plug-and-play solution for connecting large ASICs to linear optics.
The collaboration simplifies the deployment of Linear Pluggable Optics (LPO), Near Package Optics (NPO), and Co-Packaged Optics (CPO) by leveraging TSLink’s advanced link training and diagnostics and silicon-proven Synopsys 112G Ethernet PHY IP. Data center architects can connect ASICs to the optical modules that incorporate both the TeraSignal TSLink interconnect to optimize link settings and Synopsys 112G PHY IP for highest signal integrity. Supporting both PCIe 64Gb/s and Ethernet 106Gb/s standards, the protocol-agnostic TSLink supports high-speed data transmission, broad applicability, and seamless integration for AI and high-performance computing environments.
A Paradigm Shift in AI Connectivity
“The rapidly evolving architectures of hyperscalers require optical interconnects to provide low power and high bandwidth to scale AI networks,” said Neeraj Paliwal, senior vice president of IP product management at Synopsys. “With TeraSignal’s TSLink and Synopsys’ 112G Ethernet IP, designers can access proven, interoperable technologies to enable high-performance connectivity for next-gen optical modules.”
“Terasignal’s TSLink technology seamlessly integrates with Socionext’s custom SoCs to provide an optimized system, empowering the development of application-specific solutions delivering differentiating performance across LPO, NPO, and CPO optical modules,” stated Rajinder Cheema, Corporate Senior Vice President, Socionext Inc. “This innovation enables reduced power consumption, superior link performance, and advanced diagnostic and reliability features essential for today’s advanced data center solutions. These optimizations are especially beneficial for high-performance applications such as data center switching, AI inference, and machine learning.”
“Interoperability between TeraSignal’s TSLink and Synopsys’ 112G Ethernet PHY IP sets a new benchmark for intelligent interconnects,” said Dr. Armond Hairapetian, Founder and CEO of TeraSignal. “This collaboration features a protocol-agnostic, plug-and-play solution for high-speed optical connectivity, reducing design risk and advancing AI and data center infrastructure.”
Optimized Link Performance
The use of TSLink protocol-agnostic design eliminates the need for DSPs, reducing power consumption by 50% and minimizing latency. Its real-time link diagnostics and advanced monitoring capabilities ensure maximum signal integrity, delivering reliable, high-speed data transmission for compute-intensive applications.
Live Demonstration at DesignCon 2025
The TSLink solution and Synopsys 112G Ethernet PHY IP interoperability demonstration will be featured at DesignCon 2025, January 28-30, in Santa Clara, Calif. Broader TSLink reference designs, complete with TSLink firmware and the TS8401/02 Intelligent Re-Driver, will be available later this year. For more information, visit www.terasignal.com.
About TeraSignal
TeraSignal is a leader in high-speed data transmission, specializing in intelligent interconnect solutions for AI-centric data centers, and next generation computing hardware, and Linear Optics. Our technologies and products focus on improving power efficiency, reducing latency, and lowering bit-error-rate, while providing advanced link diagnostics in optical interconnects. Through innovations in CMOS design and adaptive link training, TeraSignal is redefining intelligent optical connectivity across various components in AI infrastructure. Learn more at terasignal.com.
