Tewksbury, MA – June 15, 2022 – Avery Design Systems, a leader in functional verification solutions, today announced comprehensive support for the new UCIe (Universal Chiplet Interconnect Express) standard, providing an efficient approach to enable design and verification engineers to leverage the recently-introduced standard for die-to-die interface connectivity. Avery’s offering includes high-quality models and test suites that support pre-silicon verification of systems using UCIe.

As part of the support for the standard, Avery has joined the UCIe consortium which administers the specification, and includes founding members: Intel, AMD, Arm, … Read More → "Avery Design Systems Announces Verification Support for New UCIe standard, Accelerating Adoption of Chiplet Interconnect Protocol"

Highlights:

• 20+ design wins awarded by leading semiconductor and system companies
• Multiple first-pass silicon successes achieved with Cadence IP
• IP silicon tested and characterized to ensure robust system interoperability
• Early N3 and N4 customer engagements underway

SAN JOSE, Calif., June 15, 2022—Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced a wide range of leading semiconductor and system customers have successfully adopted the comprehensive line-up of Cadence® Design IP in TSMC’s industry-leading 5nm process technology. Designed to the latest state-of-the-art interface standards, the Cadence’s Design IP portfolio enables customers to develop the most … Read More → "Cadence Design IP portfolio in TSMC’s N5 Process Gains Broad Adoption Among Leading Semiconductor and System Companies"