GiDEL Announces the Availability of TotalHistory™ a New Level in ASIC Prototyping and FPGA Debug
Kane Computing are pleased to announce that GiDEL has recently launched TotalHistory™, the most advanced debugging feature available in today’s ASIC Prototyping solutions and FPGA based systems.
TotalHistory is a software only solution enabling users to define a list of signals in the design which they want to trace at full system speed. There is practically no limit on the number of signals traced. The user can then view the trace using a waveform viewer to debug and validate the design. Optionally, an API is available for queries by advanced users.

