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World’s Lowest-Cost Ethernet AVB End-Point Solution Eliminates Barriers for New A/V Standard

Bristol, UK and Sunnyvale, Calif. – Oct. 27th, 2010– XMOS® and Attero Tech today announced a joint reference design for audio/visual bridging (AVB) applications, featuring the industry’s lowest cost solution for Ethernet AVB endpoints. The low-cost XCore® XS1-L2 dual-core processor is at the heart of the new reference design.

The development of new standards, such as AVB, needs technology that can be adapted quickly. XCore processors … Read More → "World’s Lowest-Cost Ethernet AVB End-Point Solution Eliminates Barriers for New A/V Standard"

AdaCore releases GPS 5.0

NEW YORK, PARIS and FAIRFAX, Va., October 26, 2010 – SIGAda 2010 – AdaCore, a leading supplier of Ada language tools and support services, today announced the release of GNAT Programming Studio (GPS) 5.0. This new major version of AdaCore’s graphical Integrated Development Environment (IDE) offers enhanced support for C and C++, more powerful source editing, simpler use, and integration of GNATstack (a static analysis tool that determines a program’s maximum stack requirements). GPS is provided with GNAT Pro on most platforms, for both … Read More → "AdaCore releases GPS 5.0"

Synopsys Power-Aware Test Speeds Time to Volume Production at Realtek

MOUNTAIN VIEW, Calif., Oct. 26 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Realtek Semiconductor Corporation, one of the world’s leading network and multimedia IC providers, deployed Synopsys power-aware test to avoid power issues during test and accelerate production testing of its new digital media processor.  Excessive power consumption during manufacturing test leads to overheating, IR drop, and other effects that can cause devices to fail, impacting profitability and delaying production ramp.  Designers at Realtek avoided these issues by reducing the device power consumption … Read More → "Synopsys Power-Aware Test Speeds Time to Volume Production at Realtek"

Alibre Launches Next Generation 3D Design Software — Alibre Design 2011

Richardson, TX, October 26, 2010 – Alibre Inc. www.alibre.com, the award-winning developer of the world’s most affordable professional 3D design solutions, today announced a huge leap in 3D CAD design performance with the release of its latest version, Alibre Design 2011. Alibre Design 2011 now makes 3D designing easier and more robust with major enhancements, including a complete top to bottom code re-write, native 64-bit version, powerful sheet metal conversion tools, and a myriad of time saving tools … Read More → "Alibre Launches Next Generation 3D Design Software — Alibre Design 2011"

EMA Adds Virtual Classroom Training for OrCAD, PSpice, and Autodesk Users

Rochester, NY (October 26, 2010) – EMA Design Automation™ (www.ema-eda.com), a full-service provider of electrical and mechanical CAD tools, today announced Virtual Classroom Training – combining the experience of instructor-led classroom training with the convenience of online training for Cadence® OrCAD® and PSpice ® PCB design tools, and Autodesk® mechanical CAD tools. “Aggressive time to market project schedules are forcing end users to find creative ways to invest in learning,” said Manny Marcano, president and CEO of … Read More → "EMA Adds Virtual Classroom Training for OrCAD, PSpice, and Autodesk Users"

Himax Standardizes on Synopsys Implementation, Verification and IP Solutions for Video SoC Products

MOUNTAIN VIEW, Calif.Oct. 25 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, today announced that Himax Technologies, Inc., a leading provider of advanced semiconductors for flat panel displays, has selected Synopsys’ Galaxy™ Implementation and Discovery™ Verification Platforms for its video system-on-chip (SoC) products. As part of an expanded business agreement to establish Synopsys as its primary EDA partner, Himax has also extended its use of Synopsys DesignWare® IP.

“ … Read More → "Himax Standardizes on Synopsys Implementation, Verification and IP Solutions for Video SoC Products"

Expert Static Timing Users Share Results About Latest Synopsys Timing Innovation — PrimeTime HyperScale Technology

MOUNTAIN VIEW, Calif.Oct. 21 /PRNewswire/ — Synopsys, Inc. (Nasdaq: SNPS), a world leader in software and IP for semiconductor design, verification and manufacturing, will host a PrimeTime® Special Interest Group (SIG) event in Silicon Valley unveiling the latest user results with Synopsys’ PrimeTime HyperScale Technology, the next-generation static timing analysis (STA) solution for large-chip hierarchical design. Speakers include timing experts from AMD, NVIDIA and others.

To register to attend this event, or for additional information, please visit: Read More → "Expert Static Timing Users Share Results About Latest Synopsys Timing Innovation — PrimeTime HyperScale Technology"

Nomor Research GmbH and Agilent Technologies Inc. Provide Solution to Generate LTE Uplink Inter-cell Interference Signals for LTE Field Trials and Performance Tests

Munich, Germany and SANTA CLARA, Calif., October 22, 2010 – Nomor Research GmbH and Agilent Technologies Inc. (A) today announced the availability of a simple cost-effective method for generating realistic LTE uplink inter-cell interference signals required for LTE field trials by using Agilent’s MXG signal generators. This is the most cost-effective cellular interference signal generation method available for engineers who need to validate LTE system performance under real-world signal conditions.

Nomor Research has developed a method for generating realistic inter-cell interference signals using off-the-shelf signal generators for performance testing in LTE field trials and lab tests. Realistic emulation … Read More → "Nomor Research GmbH and Agilent Technologies Inc. Provide Solution to Generate LTE Uplink Inter-cell Interference Signals for LTE Field Trials and Performance Tests"

Carbon Design Systems Launches IP Web Portal to Streamline Access to Virtual Platform Building Blocks

ACTON, MASS. –– October 21, 2010 –– Carbon Design Systems™ today unveiled Carbon IP Exchange, a web portal with a rich library of system-level models from a variety of intellectual property (IP) vendors to streamline the creation of virtual platforms for architecture analysis, performance optimization and pre-silicon software development.

The portal, used with Carbon SoC Designer Plus and SystemC-based platforms, eliminates the virtual platform assembly bottleneck by offering models for the majority of third-party IP content used in … Read More → "Carbon Design Systems Launches IP Web Portal to Streamline Access to Virtual Platform Building Blocks"

Verific Joins Cadence Connections Program

ALAMEDA, CALIF. –– October 20, 2010 –– Verific Design Automation, supplier of de facto standard SystemVerilog and VHDL front-end software to the electronic design automation (EDA) and semiconductor community, announced today that it has become a member of the Cadence Design Systems Connections® program. 

Cadence®  Connections is a program that enables interoperability between EDA software.  As a member of this program, Verific has access to Cadence software and support to ensure SystemVerilog and VHDL interoperability between Cadence products and the EDA tools that incorporate Verific’s … Read More → "Verific Joins Cadence Connections Program"

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