DRESDEN, Germany–(BUSINESS WIRE)–Aldec, Inc. has launched the latest version of its high-performance, mixed-language verification tool, Riviera-PRO™. Unveiled at the Design, Automation and Test in Europe (DATE) conference, Riviera-PRO release version 2012.02 supports a number of advanced verification methodologies which are set to greatly benefit the designers of complex FPGAs and those migrating to ASIC.
New to version 2012.02 of Riviera-PRO are support for the verification environments constructed with the Universal Verification Methodology (UVM) class library and new SystemVerilog IEEE 1800-2009 and VHDL IEEE 1076-2008 constructs. … Read More → "Aldec Takes FPGA & ASIC Debugging to the Next Level"

