Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area
SAN JOSE, CA–(Marketwire – June 27, 2012) – “The complete Cadence Encounter RTL-to-GDSII flow allowed us to tape out a complex 32-nanometer SoC design and achieve significant and meaningful improvements in power, performance and area,” said Chan Lee, vice president of VLSI engineering at Ambarella. “The Clock Concurrent Optimization (CCOpt) technology alone saved us weeks of manual work by allowing us to optimize clocks and datapaths at the same time, while still delivering excellent results in power, performance, and area.”Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader … Read More → "Cadence Encounter Digital Technology Provides Ambarella With Big Improvements in Power, Performance and Area"

