SAN JOSE, CA–(Marketwire – July 18, 2012) – Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, announced today that Renesas Electronics Corporation, a premier provider of advanced semiconductor solutions, significantly improved power, area and productivity by using Cadence® Encounter® digital technology to tape out its new generation of automotive 32-bit microcontrollers (MCU). These latest MCUs were designed specifically for integrating system control and network processing functions of car infotainment devices on one chip.

In modern MCU designs, clock networks can contribute … Read More → "Cadence Encounter Digital Technology Helps Renesas Gain Advantage in Design Power, Area and Productivity"

SAN JOSE, CA–(Marketwire – July 17, 2012) – Timing signoff closure has become an increasingly significant bottleneck due to the increase in modes and corners required for analysis and the divergence of timing results between implementation and signoff timing tools. Furthermore, the complexity of today’s designs requires the ability to do complete physically-aware MMMC signoff during ECO for rapid timing closure. To accomplish this requires a deep integration between physical and signoff design tools and a fundamentally new approach to software architecture. All of this can be done today uniquely with Cadence Encounter Timing System. The Encounter Timing System’s physically … Read More → "Fujitsu Semiconductor Selects Cadence Signoff Solution for Its Newest Reference Design Flow"

Napa, Calif., USA, 16 July 2012 — Accellera Systems Initiative announces the release of version 2.3.0 of its SystemC open source proof-of-concept library, now available at no charge to the worldwide electronic design community. Compatible with the newly revised IEEE 1666 “Standard SystemC Language Reference Manual,” announced by the IEEE Standards Association in November 2011, version 2.3.0 provides a number of important new features, including support for transaction-level modeling (TLM), a critical approach to enable high level and more efficient design of complex ICs and SoCs in a single library.

New extensive process control features enable modeling of concepts such as power domains and … Read More → "Proof-of-Concept Library is compatible with IEEE Std. 1666™-2011 Standard, includes Transaction-Level Modeling"