Analog Bits Continues to Drive Innovation for 0.25 micron to 20 nm IC Designs Using Tanner EDA Schematic Capture and Layout Tools
MONROVIA, California – January 8, 2013 – Tanner EDA, the catalyst for innovation for the design, layout and verification of analog and mixed-signal integrated circuits (ICs), has been providing schematic capture and layout solutions to Analog Bits since 1995. When Analog Bits, the leader in integrated clocking and interface IP, recently migrated their products from a 28nm to 20nm manufacturing process, Tanner EDA’s robust tools were able to meet the new layout methodology and continue to provide the usual high quality solutions.
“As process nodes shrink, electromigration is becoming a bigger and bigger problem,” said Mahesh Tirupattur, executive … Read More → "Analog Bits Continues to Drive Innovation for 0.25 micron to 20 nm IC Designs Using Tanner EDA Schematic Capture and Layout Tools"
