News – Page 1602 – EEJournal

Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process

May 22, 2013

WILSONVILLE, Ore., May 22, 2013—Mentor Graphics Corp. (NASDAQ: MENT), a leader in electronic design automation, today announced it has teamed with OpSIS and Lumerical Solutions to develop a complete EDA-style, full flow process design kit (PDK) for the OpSIS IME (Institute of Microelectronics) silicon photonics process. The prospect of integrating a silicon photonics process with silicon-based electronics would allow adding the driver and control electronics on the same chip, greatly reducing packaging complexity and cost. Adding a photonic layer and interconnects also holds the promise of solving … Read More → "Mentor Graphics Teams with OpSIS Foundries and Lumerical Solutions on PDK Development for IME Silicon Photonics Process"

TI introduces new sensorless, brushless DC motor driver to spin motors instantly

May 22, 2013

DALLAS, May 22, 2013 /PRNewswire/ — Texas Instruments Incorporated (TI) (NASDAQ: TXN) today expanded its sensorless, brushless DC (BLDC) motor driver portfolio with a new device designed for high efficiency and low noise, which requires a low external component count of only one capacitor. The DRV10963 is a 5-V, 3-phase sensorless BLDC motor driver that simplifies layout and reduces board space by 80 percent, allowing designers to create smaller, sleeker, more innovative designs. It includes integrated commutation logic, which enables instant motor spin with … Read More → "TI introduces new sensorless, brushless DC motor driver to spin motors instantly"

ATopTech’s Aprisa and Apogee Physical Implementation Tools Certified by TSMC for 16nm FinFET Technology

May 22, 2013

SAN JOSE, CA – May 22, 2013 – ATopTech, the leader in next-generation physical design solutions that address the challenges of designing integrated circuits (ICs), today announced that Aprisa™ and Apogee™, the company’s place and route solution, have been certified by TSMC for 16nm FinFET v0.1 design enablement. TSMC’s leading 16nm FinFET technology offers improved design performance, lower overall power, and smaller area.

Aprisa and Apogee were certified in October 2012 by TSMC for 20nm design enablement with double patterning technology (DPT) routing rule support for TSMC’s 20nm reference flow. … Read More → "ATopTech’s Aprisa and Apogee Physical Implementation Tools Certified by TSMC for 16nm FinFET Technology"

EEMBC and VOLKSWAGEN to Develop Benchmarking Standards to Quantify Microcontroller Energy Efficiency

May 21, 2013

El Dorado Hills, Calif. and Wolfsburg, Germany — May 21, 2013 — The Embedded Microprocessor Benchmark Consortium (EEMBC) today announced an expanded working group project with the Volkswagen Group to establish an energy-efficiency benchmark for microcontrollers aimed at making automotive end products more energy aware and more robust.

With increasing fuel costs, there is a growing emphasis on reducing energy consumption and improving fuel economy in automobiles. Simultaneously, there is also an on-going … Read More → "EEMBC and VOLKSWAGEN to Develop Benchmarking Standards to Quantify Microcontroller Energy Efficiency"

Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5/3D-ICs

May 21, 2013

WILSONVILLE, Ore., May 20, 2013—Mentor Graphics Corp. (NASDAQ: MENT) and Tezzaron Semiconductor Corp. today announced they are collaborating to integrate the Mentor® Calibre® 3DSTACK product into Tezzaron’s 3D-IC offerings. The new integration will focus on fast, automated verification of die-to-die interactions in 2.5D and 3D stacked die configurations by verifying individual dies in the usual manner, while verifying die-to-die interfaces in a separate procedure with specialized automation features. The two companies plan to extend their collaboration to include development of solutions for the silicon photonics market.

“Tezzaron specializes in 3D wafer stacking and TSV … Read More → "Mentor and Tezzaron Optimize Calibre 3DSTACK for 2.5/3D-ICs"

Imec and GLOBALFOUNDRIES collaborate to advance high-density memory technology

May 21, 2013

Leuven (Belgium) – May 21, 2013 – Imec and GLOBALFOUNDRIES announced today that they have expanded joint development efforts to advance STT-MRAM (spin-transfer torque magnetoresistive random access memory) technology.

The first IC manufacturer to join imec’s R&D program on emerging memory technologies, GLOBALFOUNDRIES completes the value chain of imec’s research platform, which fuels industry collaboration from technology up to the system level. GLOBALFOUNDRIES is joining a team with a leading fabless company (Read More → "Imec and GLOBALFOUNDRIES collaborate to advance high-density memory technology"

Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List

May 21, 2013

San Jose, Calif., May 21, 2013—Altera Corporation (NASDAQ: ALTR) today announced its 28 nm Stratix® V GX FPGAs have achieved inclusion on the latest PCI-SIG® Integrators List for the PCI Express® (PCIe®) 3.0 specification (Gen3). At the most recent PCI-SIG workshop, Stratix V GX FPGAs successfully passed all PCI-SIG compliance and interoperability tests, completing inclusion for Stratix V on all three generations of the Integrators Lists for PCIe. With Cyclone V and Arria V devices included on the 1.1 (Gen 1) and 2.0 (Gen2) lists, Altera’s entire 28 nm portfolio is now … Read More → "Altera Stratix V GX FPGAs Achieve PCIe Gen3 Compliance and Listing on PCI-SIG Integrators List"

“Places2Be” project to boost European leadership around FD-SOI – the faster, cooler, simpler chip technology

May 21, 2013

3-year, €360M project involves 19 partners across Europe, led by STMicroelectronics
2 FD-SOI manufacturing pilot lines to be located in Grenoble and Dresden
Places2Be is supported by the ENIAC JU and the National Public Authorities

Brussels, May 21 2013 – The launch of Places2Be, a 3-year, €360M advanced-technology pilot-line project to support the industrialization of Fully-Depleted Silicon-On-Insulator (FD-SOI) microelectronics technology was announced today by a group of 19 leading European companies and academic institutions.

Led by STMicroelectronics (NYSE: STM), a global semiconductor leader serving customers across the … Read More → "“Places2Be” project to boost European leadership around FD-SOI – the faster, cooler, simpler chip technology"

New Release of Cypress’s PSoC® Designer™ IDE Speeds and Simplifies Embedded Designs

May 21, 2013

San Jose, Calif., May 21, 2013 – Cypress Semiconductor Corp. (NASDAQ: CY), today introduced PSoC^® Designer™ 5.4, a new version of its Integrated Design Environment (IDE) for the PSoC 1 Programmable System-on-Chip architecture. The new version includes over 40 new or enhanced User Modules, which are free“Virtual Chips,” represented by an icon, that are used to integrate multiple ICs and system interfaces into a single PSoC device. Version 5.4 also … Read More → "New Release of Cypress’s PSoC® Designer™ IDE Speeds and Simplifies Embedded Designs"

Xilinx and Sumitomo Electric Collaborate on Smarter Solutions that Reduce Network CapEx and OpEx Costs

May 21, 2013

SAN JOSE, Calif., May 21, 2013 /PRNewswire/ — Xilinx, Inc. (NASDAQ: XLNX) today announced that Xilinx and Sumitomo Electric Industries, Ltd. are collaborating to bring smarter solutions to market. These solutions reduce CapEx and OpEx costs through the use of Sumitomo Electric’s Gallium Nitride (GaN) power amplifier transistors and Xilinx® SmartCORE™ IP that result in higher radio unit efficiencies. Wireless system designers using Xilinx’s SmartCORE IP can scale to support small cells to high-end macro cells, as well as active antenna systems (AAS), offering customers time-to-market advantages, lower development costs, high … Read More → "Xilinx and Sumitomo Electric Collaborate on Smarter Solutions that Reduce Network CapEx and OpEx Costs"

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