New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time
SAN JOSE, Calif., February 2, 2016?Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced the new Modus? Test Solution that enables design engineers to achieve an up to 3X reduction in test time, thereby reducing production test cost and increasing silicon profit margins. This next-generation test solution incorporates patent-pending, physically aware 2D Elastic Compression architecture that enables compression ratios beyond 400X without impacting design size or routing.
To address the challenges that come with testing designs, the Cadence® Modus Test Solution includes the following innovative capabilities:
- ?2D compression: Scan compression logic forms a physically aware two-dimensional … Read More → "New Cadence Modus Test Solution Delivers Up to 3X Reduction in SoC Test Time"

