MOUNTAIN VIEW, Calif., May 24, 2016 /PRNewswire/ — Synopsys, Inc. (NASDAQ: SNPS) today announced the availability of the industry’s first cache coherent subsystem verification solution for Arteris’ Ncore interconnect.  The Arteris Ncore interconnect is a configurable distributed heterogeneous cache coherent interconnect that enables system on chip (SoC) teams to efficiently design customized, fully coherent systems.  With Synopsys’ configurable cache coherent Network-on-Chip (NoC) subsystem verification solution, SoC teams can accelerate verification closure of their particular Arteris Ncore cache coherent interconnect configuration.

“The Arteris Ncore interconnect delivers enhanced configurability for heterogeneous … Read More → "Synopsys Delivers Industry’s First Cache Coherent Subsystem Verification Solution for Arteris Ncore Interconnect"

SAN JOSE, CA – May 24, 2016 – Typically, there are three phases in custom design flows where time to final layout has been a bottleneck: area estimation, layout / simulation cycle and final layout. Pulsic, the premier provider of physical design tools for precision design automation, will demonstrate solutions to overcome those bottlenecks at DAC 2016: Pulsic Animate™ and Pulsic Unity™ Chip Planner.

Pulsic Animate surpasses traditional approaches to automating transistor-level IC design, which have attempted to improve on portions of the design flow, but have not managed to generate near “manual-quality” layout without significant user intervention. Animate is the first complete … Read More → "Pulsic at DAC 2016: Overcoming the Traditional Bottlenecks in Transistor-level and Cell-level Custom Design Flows"