SAN FRANCISCO – International Electron Devices Meeting 2016 (IEDM) —Dec. 6, 2016— At the 2016 IEEE International Electron Devices Meeting, in a special poster session on MRAM, world-leading research and innovation hub for nano-electronics and digital technology imec presented a 8nm p-MTJ device with 100 percent tunnel magnetoresistance (TMR) and coercive field as high 1500Oe. This world’s smallest device enables the establishment of a manufacturing process for high-density spin-transfer-torque magnetic random access memory (STT-MRAM) arrays that meet the requirements of the 10nm and beyond logic node for embedded non-volatile memory applications. It also paves the way for high density stand-alone applications.

SAN FRANCISCO – International Electron Devices Meeting 2016 (IEDM) – Dec. 7, 2016 – At this week’s IEEE IEDM conference, imec, the world-leading research and innovation hub in nano-electronics and digital technologies showed for the first time a silicon (Si)-passivated germanium (Ge) nMOS gate stack with dramatically reduced interface defect density (DIT) reaching the same level as a Si gate stack and with high mobility and reduced positive bias temperature instability (PBTI). These promising results pave the way to Ge-based finFETs and gate all-around devices, as promising options for 5nm … Read More → "Imec Develops 3D-Compatible Germanium nMOS Gate stack with High Mobility and Superior Reliability"