Highlights:

• Cadence digital, signoff and custom/analog tools achieve latest DRM and SPICE certifications for TSMC 5nm and 7nm+ process technologies
• Digital, signoff and custom/analog tool capabilities improve 5nm and 7nm+ designer productivity
• Cadence library characterization tool flow supports 5nm and 7nm+ process

SAN JOSE, Calif., May 1, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced its continued collaboration with TSMC to further 5nm and 7nm+ FinFET design innovation for mobile and high-performance computing (HPC) platforms. The Cadence^® digital, … Read More → "Cadence Collaborates with TSMC to Advance 5nm and 7nm+ Mobile and HPC Design Innovation"

Full suite of Cadence digital, signoff and custom/analog IC design tools coupled with advanced IC package design and analysis tools optimized for TSMC WoW technology

SAN JOSE, Calif., May 1, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced that its full suite of Cadence^® digital, signoff and custom/analog IC design tools, along with advanced IC packaging design solutions, support the new TSMC Wafer-on-Wafer (WoW) stacking technology.

For more information on the Cadence solutions that support the TSMC WoW technology, visit Read More → "Cadence Supports New TSMC WoW Advanced Packaging Technology"

SAN JOSE, Calif., May 1, 2018—Cadence Design Systems, Inc. (NASDAQ: CDNS) today announced it has prototyped its first IP interface in silicon for a preliminary version of the DDR5 standard being developed in JEDEC. The Cadence test chip was fabricated in TSMC’s 7nm process and achieves a 4400 megatransfers per second (MT/sec) data rate, which is 37.5 percent faster than the fastest commercial DDR4 memory at 3200MT/sec. With this key milestone, SoC providers developing high-speed memory subsystems for high-end server, storage and enterprise applications can start developing their DDR5 memory subsystems now with silicon-tested PHY and controller IP from … Read More → "Cadence Prototypes First IP Interface in Silicon for Preliminary Version of DDR5 Standard Being Developed in JEDEC"