The System Level Power Workshop, co-organized and sponsored by Accellera Systems Initiative, the IEEE Design Automation Standards Committee (DASC) and Si2, will bring together members of both the user and standards communities to discuss the issues surrounding not only interoperability among tools and IP, but system level design and the creation of power models and their suitability at different levels of abstraction
When/Where
Tuesday, June 9, 2015
Design Automation Conference, Moscone Center, San Francisco, CA
1:15pm-4:30pm
Room 206
Agenda:
1:15pm: Registration and networking
1:30pm: Welcome – John Ellis, Si2
1:45pm: System Level Power Modeling Usage and Requirements Presentations from Users:
- Vita Vishnyakov, Microsoft
- Ahmad Ansari, Xilinx
- Barry Pangrle, Consultant
- TSMC
3:15pm: System Level Power Standardization
- Stan Krolikoski , Chair, DASC LP Coordination Committee
- Sushma Honnavara-Prasad, Secretary, IEEE 1801
- Vojin Zivojnovich, Chair, IEEE 2415
- Nagu Dhanwada, Chair, IEEE 2416
- Jerry Frenkil, Director Low Power, Si2 Low Power Coalition
3:45pm: Facilitated Discussion – John Redmond, Broadcom
- Perceived Standards Gaps
- Perceived Standards Overlaps
4:25pm: Closing Remarks – Shishpal Rawat, Accellera
Registration
The workshop is free to all DAC attendees, but registration is required. Register for the workshop.
For more information on Accellera
For more information on DASC
For more information on Si2
