HILLSBORO, OR – MARCH 1, 2011 – Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced that its award winning Platform Manager™ family of products has been fully qualified and released to volume production.  Coinciding with this production release is the updated PAC-Designer^® 6.0.1 design software, which enables analog and board designers to integrate a circuit board’s power management and digital board management functions into the Platform Manager device family.  In addition, eleven additional reference designs (including Fan Controller, Boundary Scan Port Linker and GPIO Expander ), specifically tested for use with the Platform Manager products, are now available.

“We are excited by the Platform Manager devices’ acceptance in the engineering community,” said Gordon Hands, Director of Marketing for Low Density and Mixed Signal Solutions.  “We are already seeing engineers include Platform Manager products into their designs because they help reduce board management costs by integrating power and digital board management functions.  In addition to reducing costs, designers are also taking advantage of other Platform Manager capabilities, such as the ability to log power supply and other board faults   Now that the Platform Manager devices are qualified and available in production quantities, we will be able to meet the growing customer demand for these products.” 

Platform Manager devices are expected to be used in a broad range of applications where the complexity of the board management functions can benefit from the integrated capabilities that they provide.  Typical applications are expected to include wireless infrastructure, networking core equipment, server, data storage and high-end industrial instrumentation. 

About the Platform Manager Family 

Named 2010 “Product of the Year” by Electronic Products magazine, the Platform Manager product family consists of two devices, the LPTM10-1247 and LPTM10-12107.  The LPTM10-1247 device can monitor 12 voltage rails and supports 47 digital I/O, while the LPTM10-12107 monitors up to 12 voltage rails and supports 107 digital I/O. Functionally, these devices include both a power management section and a digital board management section.  The power management section consists of a programmable threshold, precision differential input comparator block with an accuracy of 0.7%, a 48-macrocell CPLD, programmable hardware timers, a10-bit analog to digital converter and a trim block for the trimming and margining of supplies.  The digital board management section consists of a 640-LUT FPGA and programmable logic interface I/O. 

About PAC-Designer Design Software 

PAC-Designer 6.0.1 design software provides a GUI-based design methodology for analog engineers using intuitive dialog boxes to configure analog sections; the LogiBuilder design methodology to integrate power management functions into the on-chip CPLD; and the LogiBuilder or HDL (VHDL or Verilog) design methodology to integrate digital board management functions into the FPGA section of the Platform Manager devices.  The updated PAC-Designer 6.0.1 software now provides three free correct-by-construction IP cores to implement functions such as closed-loop margining, as well as 15 associated reference designs.  Digital designers can also use Lattice’s ispLEVER^® 8.1 design software to integrate other board management functions into the on-chip FPGA section using standard digital design methods. 

Pricing and Availability 

The new Platform Manager devices are available in commercial and industrial temperature ranges, and are available in environmentally friendly Lead-Free/Halogen-Free packages.  High volume pricing for the LPTM10-1247 device in a 128-pin TQFP package is $3.75.   

About Lattice Semiconductor 

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions.  For more information, visit www.latticesemi.com