feature article archive
Subscribe Now

Chillin’ with QuickLogic

Soft sourceless music flows through the dim-lit scene. The faint smell of incense lingers. The embedded system designer sitting back on the recliner is a relaxed subject, miles from the high-stress world of project schedules and power budgets. The white-robed researcher speaks softly through the microphone, pausing just long enough for the subject’s responses to her word-associations to be heard. “Fire”… “hot”, “Pillow”… “soft”, “Schedule”… “late”, “Water”… “clear”, “Budget”… “over”, “FPGA& … Read More → "Chillin’ with QuickLogic"

Tyranny of the Metaphor

It seems reasonable enough on the surface. There is a pile of work to be done, and one of the project manager’s duties is to analyze that pile into something more manageable – usually a schedule with a resource plan and budget. The well-meaning project manager looks to the wisdom of conventional project planning for guidance in calming the chaos. After all, project management is not a new science. For decades, (if not millennia), techniques for taming the complexity of large collaborative projects such as construction have been well understood. If we just pretend our embedded software … Read More → "Tyranny of the Metaphor"

Thinking Like Xilinx

Conventional wisdom says that Charles Dickens’s novels are so long because he was paid by the word. This is not strictly true, as his novels were published in serial form, and Dickens was paid by the installment. The net result is the same, however, as the volume of reading required to mine the gold from his classic works is legendary. Plot lines that could reasonably be summarized in a few succinct paragraphs drag on through chapter after chapter of flowery, flowing, profitable prose.

It appears sometimes that the PR professionals in FPGA and … Read More → "Thinking Like Xilinx"

SerDes Sweet Spot

Sometimes, even the experts get fooled. Anybody who is intimately familiar with the FPGA industry would probably have predicted the same thing. With the epic Godzilla versus Mothra game of marketing and product one-upsmanship raging between rivals Xilinx and Altera for the past decade, the next move is often simple to anticipate. In the most recent rounds of action: Xilinx packs a hard punch introducing low-cost Spartan-3 as the first 90nm FPGA. Altera strikes back with Stratix-II as the first 90nm high-speed, high-density flagship offering. Each side then counters with the piece they’re missing, Altera with Cyclone … Read More → "SerDes Sweet Spot"

Baby, You Can Drive My Car

Since my first car was among the least expensive available when I made my purchase, I thought I would see what innovations are available today in that class. The lowest-priced sedan in the United States (according to my non-scientific web search) is the 2006 Chevrolet Aveo, with a starting manufacturer’s suggested retail price under $10,000. It has safety features including front and side airbags. I also learned that you can, in fact, still buy a car without power windows and power door locks, but an AM/FM stereo and air conditioning are included as standard features. Not bad. More … Read More → "Baby, You Can Drive My Car"

How to Make An ASIC Prototype

At HARDI Electronics, we started working seriously with ASIC prototyping in FPGAs about five years ago, and we quickly realized what the challenges were. First, it was obvious that the prototyping system needed to have the required capacity corresponding to the gate size of the ASIC. In year 2000, that was quite a problem since maximum FPGA capacity was a couple of hundred thousand ASIC gates and the ASICs were 10-100 times larger (1-10 million gates). Since then, the FPGA gate capacity has grown significantly. Today the largest available FPGA, the Xilinx Virtex-4 LX200, has an equivalent ASIC gate capacity … Read More → "How to Make An ASIC Prototype"

Top-Flight Prototypes

It’s a lifelong dream for many people to actually fly a plane on their own. The daring, carefree, wind-in-your hair pilot personality, however, is a bit of a myth. In real life, a good pilot is more like a good engineer. You plan and check everything meticulously. You want to find and fix any potential problems before you leave the ground, because once the wheels are up, it’s too late. Imagine you’ve been taking flying lessons now for several months, and you’ve finally logged the training hours, completed all of your … Read More → "Top-Flight Prototypes"

Connecting the Dots

What happened is that our cars have evolved to become, essentially, complex, networked, embedded systems – big ones. An average car when I was a kid back in the ’70s had just a small number of electronic components – lights (yes, we all had those, but it seemed like a head or tail light was always burning out), a slick and fancy 8-track “audio system,” and possibly air conditioning — not much else. Electronics in these vehicles accounted for just a sliver of the purchase price of the car, and didn’t cause much of a ruckus … Read More → "Connecting the Dots"

The People’s RTOS

Open-source operating systems (and specifically embedded Linux) have been making big gains in the device software space. Development teams are attracted by the lack of licensing fees and contracts, lower cost of ownership, perceived portability, and broad availability of the underlying software and source code. Unfortunately, some of the mechanisms that create these attractive benefits also carry hidden (and not-so-hidden) penalties. Finding the right release (distribution), finding or creating a test suite that matches that distribution, getting support (since software that comes from nowhere has nobody answering the phones), and tracking the current and appropriate versions for your application … Read More → "The People’s RTOS"

featured blogs
Jan 17, 2019
After two interesting blogs by Yagya Mishra that explained the most popular features of the Run Plan assistant in Virtuoso® ADE Assembler , I am writing this third blog in the series to share... [[ Click on the title to access the full blog on the Cadence Community site...
Jan 16, 2019
112 Gbps Samtec Flyover'„¢ Demo Samtec'€™s Ralph Page walks us through a live demonstration of a Samtec Flyover'„¢ system which enables 112 Gbps PAM4 performance. The Credo CDR generates two ports of 31-bit PRBS data at 112 Gbps PAM4 data rates. The signal travels from...