Elephant in the Room
I got a note a few weeks ago from an engineering student: “Why does it take so long to compile my FPGA design?” This twitter-esque brevity led me to semi-consciously fire off some half-helpful standard response, to which the student replied: “My other projects… seem to compile almost immediately, but the FPGA takes forever.” A layer of the onion had peeled back. This was a student who was approaching HDL as just another programming language. To him, the step of synthesis-and-place-and-route was just another “compiler,” and he couldn& … Read More → "Elephant in the Room"

