Emulation: The Enabler for Hardware-Software Co-Verification

Using an emulator for ASIC verification holds the promise of extremely high execution speed, enabling the validation of system-level scenarios that are unthinkable with simulation farms. With MHz speeds, today’s fast emulators can crunch enough cycles to run entire software application stacks on top of an SOC and truly perform hardware software co-verification. However, having a fast and accurate model of the ASIC solves only half of the problem. Without the corresponding system-level environment to drive the design, that potential is wasted.

In-Circuit Emulation: More Painful Than Expected

Historically, the first emulators, as well as FPGA prototypes, have been deployed in in-circuit emulation (ICE) mode. By connecting to real target devices (the target system), it was believed that the behavior of the system would be as accurate as possible. However, since the emulated design would only run at a fraction of the speed of the actual silicon,speed rate adapters had to be inserted to buffer traffic between the live devices running at real speed and the design executed at lower speed.The different speed domains broke the timing relationships between the test environment (live devices) and the emulated design, thuspreventing the testing of many critical scenarios such as corner cases,burst accesses, etc. The verification team had the false impression thatthe design was functional, only to discover that after tape-out problems remained. And this is not the only drawback of an ICE deployment.