If you are a member of an SOC design team, or if you manage one, then memory is critically important to you. On today’s multicore SOC designs, more on-chip silicon is devoted to memory than to anything else on the chip and yet memory is often added as an afterthought. Don’t let that happen to your team. 

This white paper discusses the many alternatives for on-chip and off-chip memory usage that SOC designers must understand to develop successful multicore SOCs. It discusses the essentials of SOC memory organizations for multicore designs, on-chip SRAM and DRAM, local memories and caches, on-chip non-volatile memories, and memory controllers for off-chip memory. It covers the difference between 6T and 4T SRAM designs, the system design ramifications of NAND and NOR Flash ROM, and how DDR2 and DDR3 SDRAMS compare (the differences might surprise you).  

Memories of all types are crucial to the design of SOCs and they can be used in many ways, from the conventional bus-based and local memories seen in all SOC designs to multiported memories, FIFOs, and lookup tables.