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EVE Adds Support for TLM-2.0 to ZeBu Hardware-Assisted Verification Platforms

SAN JOSE, CALIF. –– June 1, 2010 –– EVE, the leader in hardware/software co-verification, today announced that ZeBu fast emulation platforms support the Transaction-Level Modeling Standard (TLM)-2.0, the Open SystemC Initiative (OSCI) interface standard for SystemC model interoperability and reuse, through a TLM-2.0 transactor adapter. 

TLM-2.0 support for ZeBu enables the creation of high-performance hybrid virtual platforms that combine SystemC and register transfer level (RTL) models, in a fully scalable, accurate and flexible manner, bridging the gap between software modeling and hardware implementation.

“The efficient debugging and analysis capabilities available with virtual prototypes enable software developers to start their work much earlier in the development cycle,” says Frank Schirrmeister, Synopsys director of marketing for system-level solutions.  “With our support of standards-based SystemC TLM-2.0 integrations with fast RTL emulation environments such as EVE ZeBu, Synopsys virtual prototyping products can extend the benefits of system-level visibility to development teams for hardware-software co-verification.”

Adding support for TLM-2.0 gives software developers and hardware verification teams an interoperable way to easily map their SoC development environments to our emulators,” remarks Lauro Rizzatti, EVE-USA’s general manager and vice president of marketing.  “It ties both ESL virtual platforms and simulation environments more closely to ZeBu and to each other, providing a standards-based methodology to reuse components for software development, hardware verification and hardware/software co-verification.” 

The TLM-2.0 transactor adapter is compatible with the OSCI TLM-2.0 standard, supporting multiple targets and initiators, blocking and non-blocking transport interfaces, and the Loosely Timed (LT), Loosely Timed Temporal Decoupled (LTD) and Approximately-Timed (AT) coding styles. 

At the system level, users can integrate the TLM-2.0 transactor adapter with Electronic System Level (ESL) virtual platforms, as well as with advanced SystemVerilog hardware verification environments.  At the emulator level, the ZeBu TLM-2.0 transactor adapter is an open architecture that enables interoperability with other ZeBu transactors, either from EVE’s transactor catalog or created using ZEMI-3.

EVE will demonstrate its support for TLM-2.0 in Booth #510 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim, Calif.

About EVE

EVE is the worldwide leader in hardware/software co-verification solutions, offering fast transaction-based co-emulation and in-circuit emulation, with installations at nine of the top 10 semiconductor companies.  EVE products shorten the overall verification cycle of complex integrated circuits and electronic systems designs.  Its products can be integrated with transaction-level ESL tools and software debuggers, target hardware systems, as well as Verilog, SystemVerilog and VHDL simulators.  EVE is a member of ARM, Mentor Graphics, Real Intent, Springsoft and Synopsys Partner programs.  Follow EVE on Twitter at www.twitter.com/EVETEAM.  Its United States headquarters are in San Jose, Calif.  Telephone: (408) 457-3200.  Facsimile: (408) 457-3299.  Corporate headquarters are in Palaiseau, France.  Telephone: (33) 1 64.53.27.30.  Fax: (33) 1 64.53.27.40.  Email:  info@eve-team.com.  Website:  www.eve-team.com.

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Lattice Expands Hot-Swap Application Coverage For Power Manager Devices

HILLSBORO, OR — JUNE 1, 2010 — Lattice Semiconductor Corporation (NASDAQ: LSCC) today announced the addition of a new, higher performance device to its second generation Power Manager II product family.  The ispPAC®-POWR1220-02 device integrates a higher voltage charge pump with programmable current to control MOSFETs in Hot-swap and Sequencing applications.  The new device is pin compatible with existing Power Manager II devices and integrates power management functions that typically require multiple ICs, including Hot-swap Controllers, Reset Generators, Voltage Supervisors, Sequencers and Trackers.  The ispPAC-POWR1220-02 also integrates Analog-to-Digital Converter (ADC) ICs used for power supply voltage and current measurements, and DC-DC converter trimming and margining control ICs.

“Our customers can take advantage of a significant reduction in their cost per power management function across a wide range of applications,” said Shyam Chandra, Lattice’s Mixed Signal Product Marketing Manager.  “With these increased hot-swap controller options, the Power Manager II device family can be standardized across an even wider range of systems.  With the newly updated PAC-Designer® design tool suite and User Guide, Lattice Power Manager products continue to lead the way to easier, more reliable board power designs.” 

About the Lattice PAC-Designer Tool Suite

The PAC-Designer tool suite provides design and verification tools for Lattice mixed signal devices.  The PAC-Designer software is a complete design environment, including everything needed for design, implementation, simulation and programming of supported devices.

Support for the new ispPAC-POWR1220-02 is included in the updated PAC-Designer version 5.3.  In addition to the new device support, a comprehensive PAC-Designer software User Guide is now available for download.

Pricing and Availability

Lattice’s PAC-Designer software for Windows is available now at no charge for download from the Lattice website, http://www.latticesemi.com/pac-designer.  In addition, a new comprehensive software User Guide is now available for download at the same location.

Volume (250KU+) pricing for the ispPAC-POWR1220AT8-02 device in a 100-pin TQFP package and industrial temperature range is $3.05.  Samples are available now.

About the Lattice Power Manager Family

Lattice Power Manager devices deliver highly accurate, flexible and low cost solutions for power supply and processor/DSP management.  By integrating a versatile PLD core with Analog-to-Digital (ADC) converters, Digital-to-Analog Converters (DAC), differential sense analog monitors, I2C communication and in-system programmability, Lattice Power Manager devices increase board reliability, decrease component count and help cut costs.

The current generation of Lattice’s Power Manager technology includes five devices: the POWR1220AT8, POWR1014/A, POWR607, POWR6AT6 and ProcessorPM™ devices.  All five devices are production qualified.  

About Lattice Semiconductor

Lattice is the source for innovative FPGA, PLD, programmable Power Management and Clock Management solutions.  For more information, visit www.latticesemi.com

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