Progress to smaller FPGA process geometries has led to shrinking noise margins and lower voltages. These changes mandate higher currents, tighter voltage tolerances, and management of multiple power rails. Every board designer has to learn how to deliver clean power to the FPGA, as making the wrong choice can severely reduce functionality and performance.

This webcast shows a scientific way to design an effective power distribution network (PDN) on high-end FPGAs while minimizing board complexity, decoupling requirements, and system costs.

View this webcast to learn:

• Decoupling schemes for an effective PDN design
• Factors affecting PDN design
• Altera’s PDN tool and design flow, including a design example based on the Stratix^® IV FPGA Development Kit
• Competitive comparison on bypassing requirements