Increasing bandwidth requirements for broadband services are driving silicon vendors to use more and more high-speed serial transceivers. Therefore, next-generation applications feature a wide range of data rates, from a few Mbps to hundreds of Gbps, and integrate multiple protocols and services in a single box. Quickly evolving standards like Ethernet plus the need for increasing data rates make high-speed transceivers a major decision criterion. Standard cell ASICs and ASSPs often do not provide the needed flexibility, and the cost and risk are prohibitive for many customers who must keep up with technology innovation. This paper describes how a full spectrum of 40-nm FPGAs and ASICs with transceivers addresses the challenges in next-generation systems by leveraging the advantages of leading-edge technology and reusing innovations of previous generations.
Introduction
The Internet, in its modern form, is only a little over a decade old, yet it has become the main driver for technology innovation and bandwidth growth. The need for higher bandwidth and data rates is driven largely by the demand to upgrade existing communications systems and the emergence of new applications. Today, web downloads—dominated by video—and point-to-point networks (file sharing) consume 80 percent of the bandwidth. New applications like streaming media (video-on-demand movies and television), voice-over-IP, and Internet gaming are still in the single digits. By that standard, the Internet is still in its infancy and should see strong and undamped growth.
Recent market announcements have covered communication equipment moving to 40- and even 100-GbE ports to achieve higher bandwidth with lower cost, lower power, and a more compact size. In addition, Moore’s Law still drives the semiconductor industry to double with the number of transistors in an integrated circuit every two years. The next generation of products uses the 45-nm or 40-nm process to integrate more functions, higher operating performance, logic density, and lower power per function, but the key to meeting the increasing demand for bandwidth is more and faster high-speed serial transceivers.
This paper covers the trends for high-speed serial transceivers and the challenges that system architects and designers face. It reviews specific market requirements and shows that in order to meet these requirements, PLD vendors must provide a broad portfolio of devices with transceivers. By covering a full range of logic densities, features, and I/O capabilities, these devices allow customers to develop products that meet their diverse performance, power, and cost targets.
High-Speed Transceiver Technology Trends
Higher bandwidth and higher data rates are achieved by increasing the data rates of high-speed serial transceivers and increasing the number of transceivers on a device. An interface with 100G bandwidth can be created using 10 10.3-Gbps transceivers (CAUI), 20 6.375-Gbps transceivers (Interlaken), 40 3.125-Gbps transceivers (XAUI), or 100 1.25-Gbps transceivers (SGMII, note this is for illustration purposes only and is not practical). Considering the need for two ports per device for a full egress and ingress data paths, the number of transceivers can easily exceed the physical limits of even the most modern process technologies if the data rate of the transceivers does not scale accordingly.
Author: Bernhard Friebe, Product Marketing Manager
