Actel’s flash-based FPGAs are the low-power leaders in the industry. In addition to utilizing low-power attributes of flash-based FPGAs, you can deploy several design techniques to further reduce overall power.
This application note describes various design techniques to help reduce dynamic power and accomplish this goal easily, presenting several coding scenarios with real-world results. This application note assumes that you are familiar with Actel flash FPGA architecture.
This document is organized in various sections:
• “Power Components and Dynamic Power”
• “Using SmartPower to Compute FPGA Power Profile”
• “Recommended Design Flow for Low-Power Designs”
• “Standard Techniques for Lowering Dynamic Power”
• “General Tips During Synthesis and Place-and-Route”
• “General Design Practice”
