Introduction

Moore’s law continues to drive both chip complexity and performance to new highs every year, and continues to stress and periodically “break” existing design flows. Fortunately for EDA users, the same shrinking geometries that make their design problems tougher are also helping to improve the performance for their EDA tools.

But when it comes to functional verification, traditionally the largest bottleneck in the design process, software-based approaches like simulation continue to lose ground. Why isn’t simulation speed keeping pace with device complexity? Because many new devices like 3G cell phones, internet routers, image processors, etc. require massive verification sequences that would take many CPU-years to simulate on even the fastest PC. These sequences are often a result of the need to run long, contiguous, serial protocol streams or complex embedded software in order to fully verify a new SoC or system design.