This year at DVCon US, Mentor is going to add some sizzle to our booth (#1005) during the exhibit hours. In addition to our stellar demo staff who are always available to answer questions and show you the latest capabilities of our tools, ...
Closing code coverage with a hardware-aware HLS-to-RTL flow How to be Smart About DFT for AI Chips Verification’s Next Steps: Portable Stimulus and You Chasing Reliability In Automotive Electronics Deep Learning in the Semiconductor Space Closing code coverage with ...
IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2018 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I examined IC/ASIC project verification technology adoption ...
Engineering is very involved with unforeseen roadblocks. What happens when one of these forks in the road sets you back? You have to make up time somewhere in the schedule you committed to. It’s been documented by several industry surveys that ...
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Mentor Chalk Talks
Understanding Power-Aware Simulation
Considering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation.
Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations”
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins.
Click here for more information about HyperLynx Design Rule Checking (DRC)
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”