Performing volume scan diagnosis on today’s large, advanced-node designs puts outsized demands on turn-around-time and compute resources. Mentor offers a technology called dynamic partitioning that will maximize diagnosis throughput while performing ever more demanding volume scan diagnosis. The ...
By Shelly Stalnaker – Mentor, A Siemens Business Someone once said to me, “You don’t have to be smart to learn; you just need a curious mind.” Truer words were never spoken! I get to learn so ...
Mentor, a Siemens Business is a Platinum Sponsor for this year’s Design Automation Conference (DAC). The 57th Design Automation Conference (DAC) executive committee, together with ACM and IEEE, have decided to move DAC 2020 to a virtual event format scheduled ...
Ambarella used the Tessent software Safety ecosystem to successfully meet in-system test requirements and achieve ISO26262 automotive safety integrity level (ASIL) goals for its CV22FS and CV2FS automotive camera SoCs. (Read the news release here.) Now Ambarella and Mentor ...
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Mentor Chalk Talks
Keeping Your Linux Device Secure — Mentor
Embedded security is an ongoing process, not a one-time effort. Even after your design is shipped, security vulnerabilities are certain to be discovered – even in things like the operating system. In this episode of Chalk Talk, Amelia Dalton chats with Kathy Tufto from Mentor – a Siemens business, about how to make a plan to keep your Linux-based embedded design secure, and how to respond quickly when new vulnerabilities are discovered.
Click here for more information about Mentor Embedded Linux®
Understanding Power-Aware Simulation
Considering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation.
Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations”
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins.
Click here for more information about HyperLynx Design Rule Checking (DRC)