By David Abercrombie, Rehab Kotb Ali, Ahmed Hamed-Fatehy – Mentor, A Siemens Business SADP, SAQP, and SALELE all have pros and cons for manufacturing at advanced nodes. We explain the differences so you can make the best choice for new technologies&...
We’re happy to give you a special Christmas (or whatever gift-giving holiday you may celebrate this time of year) present: the December issue of Verification Horizons! In addition to a fun look at how the Harry Potter books and ...
At their recent Open Innovation Platform (OIP) Ecosystem Forum held in Santa Clara, CA, TSMC named Mentor as their OIP Partner of the Year in four categories during the awards luncheon: Joint Development of 6nm Design Infrastructure Joint Delivery of SoIC ...
Figure 1 – Routing comparison PCB design is typically the last step in the development of an electronic product. As such, what was a well thought out schedule for each phase of the design results in the PCB layout time ...
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Mentor Chalk Talks
Understanding Power-Aware Simulation
Considering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation.
Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations”
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins.
Click here for more information about HyperLynx Design Rule Checking (DRC)
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”