Formal and High Level Synthesis Siemens partners with Arm on Automotive Electronics Design Can smart sensor systems anticipate and avoid danger? Overcoming Design Challenges with Simulation Divided on System Partitioning Formal and High Level Synthesis SemiWiki Mentor provides sequential logic equivalence ...
Next week, the biggest event in the world of embedded systems – Embedded World – takes place in Nuremberg, Germany. This is a very large trade show and associated technical conferences. I have participated in Embedded World almost every year since ...
My latest video blog is now available. This time I am looking at low power CPU modes and what is involved in using them. You can see the video here or here: Future video blogs will continue to look at topics ...
By Claudia Relyea, Revanth Reddy Pappireddy, and Sandeep Koranne – Mentor, A Siemens Business Analog/RF designers need both the speed of rule-based PEX, as well as the capacity and performance of a field solver to accurately extract MIM/MOM capacitors. ...
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Mentor Chalk Talks
Understanding Power-Aware Simulation
Considering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation.
Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations”
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins.
Click here for more information about HyperLynx Design Rule Checking (DRC)
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”