An improvement to BIST improves test coverage and time to improve functional safety of automotive ICs The growth of electronics in automobiles has spurred significant innovation in the development of advanced safety mechanisms for all the electrical and electronic systems in ...
As I have been using C for over 30 years, I am glad that it is still very popular among embedded developers. Somehow, it has never been usurped by C++; it is unclear whether other languages, like Rust, might gain a greater ...
In early February, I had the honor of keynoting the FPGA-forum held in the beautiful city of Trondheim, Norway. This is a yearly event serving both the Norwegian and European FPGA community and attracts FPGA-designers, project managers, technical managers, researchers, final ...
Late last week you may have seen the open letter from our CEO, Tony Hemmelgarn, laying out the steps that Siemens Digital Industries Software is taking to support our customers during the COVID-19 global crisis. All of us are getting ...
Mentor on Facebook
Mentor on Twitter
Mentor Chalk Talks
Understanding Power-Aware Simulation
Considering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation.
Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations”
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins.
Click here for more information about HyperLynx Design Rule Checking (DRC)
Addressing Challenges with Large SerDes System Designs
The latest high-speed SerDes standards put high demands on PCB design. In this episode of Chalk Talk, Amelia Dalton chats with Cristian Filip of Mentor about best practices and tools you can apply to implementing and validating the SerDes design on your next circuit board.
Click here for more information about SerDes Channel Design and Analysis.
Click here to register for a seminar entitled “New Solutions for Large-Scale SerDes System Design and Verification.”