Mentor Blog
August 31st
What is a UVM transaction? A transaction in UVM is a class with properties for the signals, such as address and data, plus extra information such as errors or delays. This is great for sending in one piece of stimulus, but ...
August 22nd
Calibre nmLVS-Recon to streamline IC circuit verification Design and verify 5G systems, part 1 Running With O-RAN AV Transformation Design and Verification Turbocharges OEMs Mapping Neurons to a Model Calibre nmLVS-Recon to streamline IC circuit verification ElectronicSpecifier.com In this article, ...
August 20th
Siemens raises Capital to full E/E design level Why Go Custom in AI Accelerators, Revisited Post Layout Simulation Is Becoming The Bottleneck For Analog Verification Real time operating systems: black box or open source? How to gain a competitive edge ...
August 13th
In a new technical paper, Ron Press, the director of technology enablement for the Tessent Test Solutions, describes the new TCA capability in Tessent TestKompress. The world of ATPG just changed with the introduction of a new way to create and ...
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Mentor Chalk Talks
Keeping Your Linux Device Secure — Mentor
Embedded security is an ongoing process, not a one-time effort. Even after your design is shipped, security vulnerabilities are certain to be discovered – even in things like the operating system. In this episode of Chalk Talk, Amelia Dalton chats with Kathy Tufto from Mentor – a Siemens business, about how to make a plan to keep your Linux-based embedded design secure, and how to respond quickly when new vulnerabilities are discovered. Click here for more information about Mentor Embedded Linux® |
Understanding Power-Aware SimulationConsidering power delivery and signal integrity separately can lead to suboptimal results in PCB design. Signal return paths can interact with power delivery networks in a number of ways, and power-aware analysis can help identify and correct problems before you build your prototype. In this episode of Chalk Talk, Amelia Dalton chats with Todd Westerhoff of Mentor about power-aware simulation. Click here to download the whitepaper “Power-Aware: Ensuring DDRx Design Reliability by Integrating Signal Integrity and Power Integrity Simulations” |
Shift Left for Fewer PCB Re-Spins
Design rule checking (DRC) is becoming more important with today’s complex PCB designs. With the complexity of today’s designs, the old ad-hoc methods just don’t cut it. In this episode of Chalk Talk, Amelia Dalton chats with Rory Riggs from Mentor about how Hyperlynx DRC can help get your next design out on time without those pesky re-spins. Click here for more information about HyperLynx Design Rule Checking (DRC) |