Henderson, NV, USA – September 9, 2019 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA, ASIC and SoC designs, has enhanced its HES Proto-AXI™ software to provide even greater support to designers using the company’s HES™ pre-silicon prototyping solution for hardware verification and software validation.
The enhancements include support for QEMU (the open source machine emulator and virtualizer) and SystemC TLM version 2.0, plus resources that increase the interoperability of HES Proto-AXI™ with third party tools.
“The addition of QEMU is of immense benefit,” says Zibi Zalewski, General Manager of Aldec’s Hardware Division. “QEMU emulates a CPU subsystem which can generate AXI transactions for the design or algorithm kernel running in a HES board. The interface can also be used during simulation when the application is under development.”
Of equal benefit is support for the latest version of SystemC TLM. This transaction-level modelling (TLM) interface is commonly adopted as the interconnect standard in Virtual Platforms that are used to model CPU subsystems for architecture exploration and early software development. This feature allows for the linking of design components, running on a HES board and connected with HES Proto AXI™ infrastructure, with the CPU sub-system running the Virtual Platform.
The latest version of HES Proto-AXI™ also features Xilinx Vivado and Microsoft Visual C++ support. Zalewski concludes: “These are all significant enhancements to an already-good environment for SoC development.”
About HES Proto-AXI™
The HES Proto-AXI™ software package, when combined with Aldec’s HES™ prototyping boards, provides an efficient and robust environment for rapid design prototyping and/or algorithm accelerator development and bring-up.
About HES™
HES™ is a SoC/ASIC pre-silicon prototyping solution for hardware verification and software validation teams. It is also a high-performance computing (HPC) platform for algorithms acceleration. The boards are based on the largest Virtex-7 and Virtex UltraScale FPGAs, appear in single or multi-FPGA configurations, and can be interconnected on a backplane board to provide for up to 663 Million ASIC gates.
About Aldec
Established in 1984, Aldec is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, High-Performance Computing Platforms, Embedded Development Systems, Requirements Lifecycle Management, DO-254 Functional Verification and Military/Aerospace solutions. www.aldec.com
