industry news
Subscribe Now

Rohde & Schwarz presents first automated solution to speed up PCIe 5.0 and 6.0 cable and connector compliance testing

For precise and time-saving compliance testing of the latest generation PCIe 5.0 and 6.0 cables and connectors in line with PCI-SIG specifications, Rohde & Schwarz is developing a new R&S ZNrun vector network analyzer automation suite option. For a fully automated verification of a PCIe x8 cable, for instance, the software controls a setup with R&S ZNB vector network analyzer plus scalable R&S OSP switch matrix configuration, creating a multiport VNA solution with 64 test ports. The solution reduces testing times for PCIe x8 cables to just a few minutes for complete test runs with all Thru and all crosstalk combinations plus corresponding metric calculations for Pass/Fail evaluations. By comparison, manual testing takes several hours and involves major risk of connection errors by test engineers.

Rohde & Schwarz efficiently tackles compliance verification challenges for PCIe 5.0 and 6.0 cables and connectors by automating the process with a new R&S ZNrun vector network analyzer automation suite option. R&S ZNrun-K440 is designed for automatic compliance testing of PCIe 5.0 and 6.0 internal and external cables and connectors in line with PCI-SIG specifications, saving users a lot of time. The test setup is based on the R&S ZNB26 or R&S ZNB43 vector network analyzer with four test ports in combination with multiple R&S OSP320 open switch and control platforms – depending on the number of the DUT lanes for verification – to provide multiple four-port measurements, all without reconnecting to the DUT and repeatedly terminating the other lanes. A PCIe x8 cable, for example, has 16 lanes and requires 64 test ports, provided by three R&S OSP320 platforms, while a PCIe x4 cable only needs 32 test ports from two R&S OSP320 platforms.

The R&S ZNrun-K440 solution fully automates all measurements in line with the PCIe specification. Postprocessing of defined PCIe metrices is also covered. A powerful test configurator lets test items be selected and deselected by lane for greater flexibility in meeting customer needs and preferences in R&D and verification testing. A test report with a pass/fail verdict is generated at the end of the automated measurement. The automation features a new calibration procedure, which significantly reduces number of calibration steps and calibration connections. It also includes a method for de-embedding of the test fixture as required in the PCIe test specifications.

Increasingly complex test demands with PCIe evolution
Each iteration of the PCIe evolution has doubled the transfer rate to meet ever increasing demand for speed. Data centers across the world are starting to use the latest versions of PCIe 5.0 and 6.0 cables to connect large amounts of high-speed data storage. Cable manufacturers are also ramping up production to deliver the first PCIe 5.0 and 6.0 cables to customers. R&D verification, compliance testing and manufacturing all require thorough testing to guarantee compliance with PCIe requirements and the proper functioning of the overall system.

Each PCIe link has 1, 2, 4, 8 or 16 lane pairs, with each lane pair consisting of one differential TX and one differential RX lane. With 8 lane pairs in a x8 configuration, a PCIe 6.0 cable can have transfer rates of up to 64 GB/s. Manually verifying compliance of high-speed interconnect is labor intensive and error prone. A total of 256 four-port measurements are needed for all Thru connections and all near-end and far-end crosstalk paths inside the cable. With traditional four-port vector network analyzers, a VNA must be reconnected for each four-port measurement and unmeasured lanes must be properly terminated. The new automated solution from Rohde & Schwarz drastically simplifies this process.

Since certain limit mask excursions are not critical for overall PCIe 5.0/6.0 system behavior, pass/fail verdicts are based on metrices such integrated return loss (iRL) and component contribution to integrated crosstalk noise (ccICN). They are defined in the PCI-SIG specification and need to be calculated from the S-parameter results and require significant postprocessing. Calibrating test fixture characterization and de-embedding brings additional challenges. R&S ZNrun-K440 software for automatic compliance testing covers them all.

Because of their importance to PCIe systems, PCI-SIG is in the process of defining standardized cables for internal (inside a chassis) and external (chassis-to-chassis) applications, including the corresponding electrical requirements for mated cable assemblies and mated cable connectors at both 32 GT/s and 64 GT/s. R&S ZN-run-K440 will also cover these PCIe tests, once they are standardized.

New solution showcased at PCI-SIG Developers Conference
Rohde & Schwarz demonstrates its new automated solution for PCIe 5.0 and 6.0 cable and connector compliance testing to members of the PCI-SIG community at the PCI-SIG Developers Conference from June 13 to 14, 2023 at the Santa Clara Convention Center in Santa Clara, CA. The new R&S ZNrun-K440 option will be available soon and complements the Rohde & Schwarz compliance test software automation portfolio. The R&S ZNrun-K410 and R&S ZNrun-K411 options are already available for high-speed Ethernet cable assemblies in line with IEEE 802.3bj, by, cd and ck.

For more information about the R&S ZNrun vector network analyzer automation suite, visit: https://www.rohde-schwarz.com/_63493-109824.html

Leave a Reply

featured blogs
Apr 23, 2024
The automotive industry's transformation from a primarily mechanical domain to a highly technological one is remarkable. Once considered mere vehicles, cars are now advanced computers on wheels, embodying the shift from roaring engines to the quiet hum of processors due ...
Apr 22, 2024
Learn what gate-all-around (GAA) transistors are, explore the switch from fin field-effect transistors (FinFETs), and see the impact on SoC design & EDA tools.The post What You Need to Know About Gate-All-Around Designs appeared first on Chip Design....
Apr 18, 2024
Are you ready for a revolution in robotic technology (as opposed to a robotic revolution, of course)?...

featured video

MaxLinear Integrates Analog & Digital Design in One Chip with Cadence 3D Solvers

Sponsored by Cadence Design Systems

MaxLinear has the unique capability of integrating analog and digital design on the same chip. Because of this, the team developed some interesting technology in the communication space. In the optical infrastructure domain, they created the first fully integrated 5nm CMOS PAM4 DSP. All their products solve critical communication and high-frequency analysis challenges.

Learn more about how MaxLinear is using Cadence’s Clarity 3D Solver and EMX Planar 3D Solver in their design process.

featured chalk talk

Battery-free IoT devices: Enabled by Infineon’s NFC Energy-Harvesting
Sponsored by Mouser Electronics and Infineon
Energy harvesting has become more popular than ever before for a wide range of IoT devices. In this episode of Chalk Talk, Amelia Dalton chats with Stathis Zafiriadis from Infineon about the details of Infineon’s NFC energy harvesting technology and how you can get started using this technology in your next IoT design. They discuss the connectivity and sensing capabilities of Infineon’s NAC1080 and NGC1081 NFC actuation controllers and the applications that would be a great fit for these innovative solutions.
Aug 17, 2023
29,712 views