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(R)evolution in I3C?

DCD-SEMI, leading IP Core provider and SoC design house from Poland mastered DI3CM-HCI controller. The IP fully supports MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification. DCD enhanced its Core with MIPI Manufacturer ID: 0x03B3.

Bytom, Poland. April the 28th, 2022. The newest DCD’s DI3CM-HCI controller has been basen on three pillars:

  • Support low-energy and high-speed
  • Reduce number of physical pins
  • To standardize sensor communication.

That’s why DCD-SEMI maintains backward compatibility, enabling a smooth transition from I2C to I3C and simple implementation. – The newest Core offers a flexible multi-drop interface between a host processor and peripheral sensors – explains Jacek Hanke, DCD-SEMI’s CEO – to support the growing usage of sensors in embedded systems. The same I3C standardizes sensor communication, reduces the number of physical pins used in sensor system integration, and supports low-power, high-speed, and other critical features that are currently covered by I2C and SPI.

Keeping the best assets from its elder brother, the I3C has major improvements in use and power, and performance. The Core uses just two pins and consumes a fraction of the energy, reducing cost and complexity while allowing multiple sensors from different vendors to be easily interfaced with a controller or application processor. The host interface of the MIPI I3C Master can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite or Custom protocol.

More information: www.dcd-semi.com 

Key features: 

  • Conforms to MIPI I3C Basic v1.1.1 specifications with Host Controller Interface v1.1 specification
  • MIPI Manufacturer ID: 0x03B3
  • Dynamic Addressing while supporting Static Addressing for Legacy I2C Devices
  • Dynamic address assignment (DAA) support
  • Legacy I2C messaging
  • I2C-like Single Data Rate messaging (SDR)
  • Master operation with FIFO:
    Master transmitter
    Master receiver
  • Supports flexible transmission speed modes:
    FAST-PLUS (up to 1000 kb/s)
    SDR (up to 12,5 Mb/s)
  • Configurable DAT/DCT size up to 16 slots
  • Configurable FIFO size
  • Interrupt generation
  • Support for In-Band Interrupts
  • Support for Hot-Join
  • Support for I3C Common Command Codes
  • Fully interoperable with third-party slave solutions
  • Fully synthesizable, static synchronous design with positive edge clocking and synchronous reset
  • Available system interface wrappers:
    AMBA – APB / AHB / AXI Bus
    Altera Avalon Bus
    Xilinx OPB Bus
  • Optional support for HDR modes

 

About DCD-SEMI

DCD-SEMI has two decades of IP market experience. The company was founded in 1999 in Bytom, Poland and has mastered more than 70 different architectures, among them the World’s Fastest 8051 CPU, Royalty-Free and Fully Scalable 32-bit CPU and 100% cryptographic system. Automotive IP Cores designed by DCD-SEMI are offered as CAN ALL package – a tailored made IP Core which have been successfully implemented by dozens of automotive companies such as VW, Toyota and now, GuardKnox. More information can be found at: www.dcd-semi.com, www.cfdsemi.com and www.crypt-one.com.

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